akm4516a.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//=====================================================================  
//    TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION             
// Property of Texas Instruments -- For Unrestricted Internal Use Only   
// Unauthorized reproduction and/or distribution is strictly prohibited  
// This product is protected under copyright law and trade secret law as 
// an unpublished work.Created 1987,(C) Copyright 1997 Texas Instruments.
// All rights reserved.                                                  
//=====================================================================  

#ifndef AKM4516A_H
#define AKM4516A_H

#include "mapping.h"



// dummy data transfered during a read codec cycle : hexa 55
#define DUMMY_DATA   0x0055

// control register frame mask 
#define OP_CODE_MASK 0xE000
#define ADRESSE_MASK 0x1F00 
#define DATA_MASK    0x00FF

// operand code value
#define WRITE_OP_CODE 0xE000
#define READ_OP_CODE  0xC000

// register address
#define INPUT_SELECT_ADDR                   (UWORD16) (0x0000 << 8)
#define MODE_CONTROL_1_ADDR                 (UWORD16) (0x0001 << 8)
#define MODE_CONTROL_2_ADDR                 (UWORD16) (0x0002 << 8)
#define ZERO_CROSS_TIMER_CONTROL_ADDR       (UWORD16) (0x0003 << 8)
#define PEAK_HOLD_LOW_BYTE_LCH_ADDR         (UWORD16) (0x0004 << 8)
#define PEAK_HOLD_HIGH_BYTE_LCH_ADDR        (UWORD16) (0x0005 << 8)
#define PEAK_HOLD_LOW_BYTE_RCH_ADDR         (UWORD16) (0x0006 << 8)
#define PEAK_HOLD_HIGH_BYTE_RCH_ADDR        (UWORD16) (0x0007 << 8)
#define OVERFLOW_STATUS_ADDR                (UWORD16) (0x0008 << 8)
#define AUTO_LMT_RCV_CONTROL_ADDR           (UWORD16) (0x0009 << 8)
#define INPUT_PGA_CONTROL_LCH_ADDR          (UWORD16) (0x000A << 8)
#define INPUT_PGA_CONTROL_RCH_ADDR          (UWORD16) (0x000B << 8)
#define AUTO_RECOVERY_CONTROL_1_ADDR        (UWORD16) (0x000C << 8)
#define AUTO_RECOVERY_CONTROL_2_ADDR        (UWORD16) (0x000D << 8)

// register bit description

//-------------------------------------------
// of INPUT_SELECT                           
//-------------------------------------------

#define LIN1 0 // Select ON/OFF of Lch input (0:OFF, 1:ON).
#define LIN2 1 // Select ON/OFF of Lch input (0:OFF, 1:ON).
#define RIN1 2 // Select ON/OFF of Rch input (0:OFF, 1:ON).
#define RIN2 3 // Select ON/OFF of Rch input (0:OFF, 1:ON).

//-------------------------------------------
// of MODE_CONTROL_1
//-------------------------------------------

#define PM0 0 //Mixer, PGA input, Auto Limitter and Auto Recovery power control (0: Power Down, 1:Power Up).
#define PM1 1 // Power control of ADC (0: Power Down, 1:Power Up) 
#define PM2 2 // Power control of DAC (0: Power Down, 1:Power Up) 
#define PM3 3 // Used both as power control of analog loopback circuit and as selection of MUX. (0: DAC, 1:Analog loopback)

//-------------------------------------------
// of MODE_CONTROL_2                         
//-------------------------------------------

#define MONO0 6 // Monaural Mixing 
#define MONO1 7 // Monaural Mixing 
                // 00: Stereo      
                // 01: (L+R)/2     
                // 10: LL          
                // 11: RR          

#define DIF0 4  //Select Audio Serial Interface Format The data is all 2's complement, MSB first.
#define DIF1 5  //Select Audio Serial Interface Format The data is all 2's complement, MSB first.
                //         SDTO(ADC)         SDTI(DAC)   
                // 0 0   MSB justified    LSB justified  
                // 0 1   LSB justified    LSB justifed   
                // 1 0   MSB justified    MSB justified  
                // 1 1   I2S compatible   I2S compatible 

#define FS0 2   // Select De-emphasis frequency for input audio data. 
#define FS1 3   // Select De-emphasis frequency for input audio data. 
                // 0 0 44.1kHz
                // 0 1 OFF 
                // 1 0 48kHz 
                // 1 1 32kHz 

#define DEM 1   // Control of De-emphasis (0: Disable, 1: Enable)


//-------------------------------------------
// of ZERO_CROSS_TIMER_CONTROL               
//-------------------------------------------

#define LRGA 7  // Selects the method of writing to IPGA
                //0: Independent data can be written to IPGA and IPGR. 
                //1: Common data can be written to IPGL and IPGR.

#define  GSEL 6 //Selects input gain (set a common Lch and Rch)
                // 0: LINE 
                // 1: MIC  

#define NRTM0 4 // Zero crossing timeout at writing operation by uP and auto recovery operation.
#define NRTM1 5 // Zero crossing timeout at writing operation by uP and auto recovery operation.
                // NRTM1 NRTM0          48kHz  44.1kHz 32kHz  
                // 0      0     513/fs  10.7ms 11.6ms  16.0ms 
                // 0      1    1025/fs  21.4ms 23.2ms  32.0ms 
                // 1      0    2049/fs  42.7ms 46.5ms  64.0ms 
                // 1      1    4097/fs  85.4ms 92.9ms  128.0ms

#define ZENM  3 // Enables zero crossing detection at uP WRITE operation or auto recovery operation (0: Disable, 1: Enable)

#define LTM0 1  // Zero crossing timeout(if ZELM="1") or Update period(if ZELM="0") at the auto limitter mode 
#define LTM1 2  // Zero crossing timeout(if ZELM="1") or Update period(if ZELM="0") at the auto limitter mode 
                //                      (ZELM="1")                (ZELM="0")       
                // LTM1 LTM0         48kHz 44.1kHz 32kHz       48kHz 44.1kHz 32kHz 
                //  0     0   129/fs 2.7ms  2.9ms  4.0ms  1/fs 21us   23us   31us  
                //  0     1   258/fs 5.4ms  5.9ms  8.1ms  2/fs 42us   45us   63us  
                //  1     0   516/fs 10.8ms 11.7ms 16.1ms 4/fs 83us   91us  125us  
                //  1     1  1032/fs 21.5ms 23.4ms 32.3ms 8/fs 167us 181us  250us  

#define ZELM 0  // Enables zero crossing detection at the auto limitter operation (0: Disable, 1: Enable) 


//-------------------------------------------
// of PEAK_HOLD_LOW_BYTE_LCH                 
//-------------------------------------------
#define PLL7 7  // Peak hold low byte of Lch (Absolute value), 8bit of LSB (FFH~00H) 

//-------------------------------------------
// of PEAK_HOLD_HIGH_BYTE_LCH                
//-------------------------------------------
#define PUL7 7 // Peak hold high byte of Lch (Absolute value), 8bit of MSB (7FH~00H) 

//-------------------------------------------
// of PEAK_HOLD_LOW_BYTE_RCH                 
//-------------------------------------------
#define PLR7 7 // Peak hold low byte of Rch (Absolute value), 8bit of LSB (FFH~00H) 

//-------------------------------------------
// of PEAK_HOLD_HIGH_BYTE_RCH                
//-------------------------------------------
#define PUR7 7 // Peak hold high byte of Rch (Absolute value), 8bit of MSB (7FH~00H)

//-------------------------------------------
// of OVERFLOW_STATUS                        
//-------------------------------------------

#define ZFIPR 7  // Rch IPGA zero crossing detection flag. 
#define ZFIPL 6  // Lch IPGA zero crossing detection flag.

#define ROF2 5   // Overflow Flag of Rch 
#define ROF1 4   // Overflow Flag of Rch 
#define ROF0 3   // Overflow Flag of Rch 
                 // ROF2-0 Threshold
                 // 0 0 0 <-12.04dB 
                 // 0 0 1 -12.04dB< 
                 // 0 1 0 -8.52dB < 
                 // 0 1 1 -6.02dB < 
                 // 1 0 0 -4.08dB < 
                 // 1 0 1 -1.80dB < 
                 // 1 1 0 -0.00dB < 

#define LOF2 2   //Overflow Flag of Lch 
#define LOF1 1   //Overflow Flag of Lch 
#define LOF0 0   //Overflow Flag of Lch 
                 // LOF2-0 Threshold
                 // 0 0 0 <-12.04dB 
                 // 0 0 1 -12.04dB< 
                 // 0 1 0 -8.52dB < 
                 // 0 1 1 -6.02dB < 
                 // 1 0 0 -4.08dB < 
                 // 1 0 1 -1.80dB < 
                 // 1 1 0 -0.00dB <