fpga_dolo.h

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

/*===============================================================================
            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
                                                                             
   Property of Texas Instruments 
   For  Unrestricted  Internal  Use  Only 
   Unauthorized reproduction and/or distribution is strictly prohibited.  
   This product is protected under copyright law and trade secret law 
   as an unpublished work.  
   Created 1999, (C) Copyright 1999 Texas Instruments.  All rights reserved.

   Filename             : fpga.h

   Description          : Dolomites DC fpga

   Project              : Dolomites DC

===============================================================================*/

#ifndef _FPGA_DOLO__HH
#define _FPGA_DOLO__HH

#include "global_types.h"

// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Base address of FPGA integrated circuit
// ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
#define FPGA_ADDR	0x09000000 //located at the middle of CS2

//
// ~~~~~~~~~~~~
//    OFFSET
// ~~~~~~~~~~~~
#define FPGA_TEST_REVISION_REG_OFFSET		    0x0
#define FPGA_APPLI_REVISION_REG_OFFSET 	    0x2
#define FPGA_APPLI_CONFIG_OFFSET 			    0x4
#define FPGA_INTERRPUT_STATUS_OFFSET		    0x6
#define FPGA_INTERRPUT_MASK_REG_OFFSET		    0x8
#define FPGA_UART_REG_OFFSET	  			       0xA
#define FPGA_TEST_CONFIG_REG_OFFSET		       0xC
#define FPGA_TEST_FLASH_REG_OFFSET			    0xE
#define FPGA_PARALLEL_PORT_DATA_REG_OFFSET    0x10
#define FPGA_PARALLEL_PORT_STATUS_REG_OFFSET  0x12
#define FPGA_PARALLEL_PORT_CTRL_REG_OFFSET    0x14
#define FPGA_RESET_REG_OFFSET                 0x16
#define FPGA_7_SEGMENTS_LED_1_REG_OFFSET      0x18
#define FPGA_7_SEGMENTS_LED_2_REG_OFFSET      0x1A
#define FPGA_7_SEGMENTS_LED_3_REG_OFFSET      0x1C
#define FPGA_LCD_ID_REG_OFFSET                0x1E
#define FPGA_TEST_EQUIP_ID_REG_OFFSET         0x20
#define FPGA_CLOCK_CONFIG_REG_OFFSET          0x22
#define FPGA_AUDIO_CONTROL_REG_OFFSET         0x24
#define FPGA_ETHERNET_REG_OFFSET              0x26
//
// ~~~~~~~~~~~~
//   ADDRESS
// ~~~~~~~~~~~~
#define FPGA_TEST_REVISION_ADDR 		    (FPGA_ADDR + FPGA_TEST_REVISION_REG_OFFSET)
#define FPGA_APPLI_REVISION_ADDR			 (FPGA_ADDR + FPGA_APPLI_REVISION_REG_OFFSET)
#define FPGA_APPLI_CONFIG_ADDR	       (FPGA_ADDR + FPGA_APPLI_CONFIG_OFFSET)
#define FPGA_INTERRPUT_STATUS_ADDR 		 (FPGA_ADDR + FPGA_INTERRPUT_STATUS_OFFSET)
#define FPGA_NTERRPUT_MASK_ADDR			 (FPGA_ADDR + FPGA_INTERRPUT_MASK_REG_OFFSET)
#define FPGA_UART_ADDR				       (FPGA_ADDR + FPGA_UART_REG_OFFSET)
#define FPGA_TEST_CONFIG_ADDR		       (FPGA_ADDR + FPGA_TEST_CONFIG_REG_OFFSET)
#define FPGA_TEST_FLASH_ADDR				 (FPGA_ADDR + FPGA_TEST_FLASH_REG_OFFSET)
#define FPGA_PARALLEL_PORT_DATA_ADDR	 (FPGA_ADDR + FPGA_PARALLEL_PORT_DATA_REG_OFFSET)
#define FPGA_PARALLEL_PORT_STATUS_ADDR  (FPGA_ADDR + FPGA_PARALLEL_PORT_STATUS_REG_OFFSET)
#define FPGA_PARALLEL_PORT_CTRL_ADDR 	 (FPGA_ADDR + FPGA_PARALLEL_PORT_CTRL_REG_OFFSET)
#define FPGA_RESE_ADDR			          (FPGA_ADDR + FPGA_RESET_REG_OFFSET)
#define FPGA_7_SEGMENTS_LED_1_ADDR	    (FPGA_ADDR + FPGA_7_SEGMENTS_LED_1_REG_OFFSET)
#define FPGA_7_SEGMENTS_LED_2_ADDR		 (FPGA_ADDR + FPGA_7_SEGMENTS_LED_2_REG_OFFSET)
#define FPGA_7_SEGMENTS_LED_3_ADDR		 (FPGA_ADDR + FPGA_7_SEGMENTS_LED_3_REG_OFFSET)
#define FPGA_LCD_ID_ADDR				    (FPGA_ADDR + FPGA_LCD_ID_REG_OFFSET)
#define FPGA_TEST_EQUIP_ID_ADDR		    (FPGA_ADDR + FPGA_TEST_EQUIP_ID_REG_OFFSET)
#define FPGA_CLOCK_CONFIG_ADDR		  	 (FPGA_ADDR + FPGA_CLOCK_CONFIG_REG_OFFSET)
#define FPGA_AUDIO_CONTROL_ADDR			 (FPGA_ADDR + FPGA_AUDIO_CONTROL_REG_OFFSET)                 FPGA_PARALLEL_PORT_STATUS_REG_OFFSET)
#define FPGA_ETHERNET_ADDR					 (FPGA_ADDR + FPGA_ETHERNET_REG_OFFSET)
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      
//
// ~~~~~~~~~~~~~~~~~~~~~~~
// REGISTER MASK DEFINITION
// ~~~~~~~~~~~~~~~~~~~~~~~
// LED_LCD register
#define	LED_MASK	                  0x00FF

// appli control register
#define IOTA_CARRIER_DETECT_MASK	   0x0001
#define IOTA_CHIP_DETECT_MASK	      0x0002
#define SHAMU_CARRIER_DETECT_MASK	0x0004
#define SHAMU_CHIP_DETECT_MASK	   0x0008
#define DOLO_CARRIER_DETECT_MASK	   0x0010
#define DOLO_CHIP_DETECT_MASK	      0x0020
#define IQ_MODE_MASK	               0x0400
#define FLASH_MODE_0_MASK	         0x0800
#define FLASH_MODE_1_MASK	         0x1000
#define FLASH_DEVICE_MASK	         0x2000

// interrupt status register
#define PP_STAT_MASK     	         0x0001
#define RI_STAT_UART1_MASK	         0x0002
#define DCD_STAT_UART1_MASK	      0x0004
#define RI_STAT_UART2_MASK	         0x0008
#define DCD_STAT_UART2_MASK	      0x0010
#define ETHERNET_STAT_MASK	         0x0020
#define SMIF_STAT_MASK	            0x0040
#define TOUCH_SCREEN_STAT_MASK	   0x0080
#define IT_EXT_STAT_MASK	         0x0100

// interrupt mask register
#define PP_MASK     	               0x0001
#define RI_UART1_MASK	            0x0002
#define DCD_UART1_MASK	            0x0004
#define RI_UART2_MASK	            0x0008
#define DCD_UART2_MASK	            0x0010
#define ETHERNET_MASK	            0x0020
#define SMIF_MASK	                  0x0040
#define TOUCH_SCREEN_MASK	         0x0080
#define IT_EXT_MASK	               0x0100

// UART register
#define UART_1_SHUTDOWN_MASK        0x0010
#define UART_2_SHUTDOWN_MASK        0x0200

// test configuration register

// reset register
#define RESET_MASK        0x0001

// test flash register

// LCD ID register
#define LCD_MASK                    0x0007

// reset register
#define N_SW_RST_MASK               0x0001

//----------------------------------------------------------------------------
// LCD ID definition
//----------------------------------------------------------------------------
#define KYOCERA_5                   0x00   
#define KYOCERA_3                   0x01
#define EPSON_L2D22                 0x02   
#define NO_LCD_CONNECTED            0x07   

//----------------------------------------------------------------------------
// 7 Segment LED Display definition
//----------------------------------------------------------------------------
#define LED_DISPLAY_0               0x80
#define LED_DISPLAY_1               0xF2
#define LED_DISPLAY_2               0x48
#define LED_DISPLAY_3               0x60
#define LED_DISPLAY_4               0x32
#define LED_DISPLAY_5               0x24
#define LED_DISPLAY_6               0x04
#define LED_DISPLAY_7               0xF0
#define LED_DISPLAY_8               0x00
#define LED_DISPLAY_9               0x20
#define LED_DISPLAY_A               0x10
#define LED_DISPLAY_B               0x06
#define LED_DISPLAY_C               0x4E
#define LED_DISPLAY_D               0x42
#define LED_DISPLAY_E               0x0C
#define LED_DISPLAY_F               0x1C
#define LED_DISPLAY_P               0x18
#define LED_DISPLAY_C2              0x8C
#define LED_1                       1
#define LED_2                       2
#define LED_3                       3
// clock configuration register
#define CLK_REF_SRC_MASK            0x0001
#define CLK_13M_SRC_0_MASK          0x0002
#define CLK_13M_SRC_1_MASK          0x0004
#define FORCE_TCXOEN_MASK           0x0008
#define AP_PHASE_0_MASK             0x000A
#define AP_PHASE_1_MASK             0x000C
#define PLL_EN_13_61_MASK           0x000E
#define PLL_EN_10_13_MASK           0x0010
#define PLL_EN_10_61_MASK           0x0012

// audio control register
#define EXT_AUD_CTRL_OUT_0_MASK     0x0001
#define EXT_AUD_CTRL_OUT_1_MASK     0x0002
#define EXT_AUD_CTRL_IN_0_MASK      0x0004
#define EXT_AUD_CTRL_IN_1_MASK      0x0008

// ethernet port
#define ETH_RESET_MASK              0x0001
#define ETH_ENEEP_MASK              0x0002
#define N_ETH_AEN_MASK              0x0004
#define N_ETH_IOWR_MASK             0x0008
#define N_ETH_IORD_MASK             0x000A
#define ETH_INT_MASK                0x000C


// functions declarations
void FPGA_write(UWORD32 reg_add, UWORD16 reg_mask, UWORD16 reg_value);
UWORD16 FPGA_read(UWORD32 reg_add);

UWORD16 FPGA_test_revision_read(void);
UWORD16 FPGA_appli_revision_read(void);
UWORD16 FPGA_LCD_ID_read(void);
UWORD16 FPGA_7_segment_led_read(UWORD16 LED_NB);
void FPGA_7_segment_led_write(UWORD16 LED_NB, UWORD16 value);

#endif