debug-macros.h.s

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

	    ; -----------------------------
char	    SETS List:LEFT:1				
	    [ (char = ",") :LOR: (:LEN:List=1)
		[ :LEN:List=1
ModeTag		    SETS ModeTag:CC:char
		]
	       
		CheckMode	$ModeTag
	    
		MRS	r0, CPSR
	    
		IF	{CONFIG} = 32

		    AND	r0, r0, #Mode_$ModeTag._32
		    CMP	r0, #Mode_$ModeTag._32
	
		ELSE

		    IF $ModeTag = "IRQ" :LOR: $ModeTag = "FIQ"

			AND	r0, r0, #Mode_$ModeTag._26
			CMP	r0, #Mode_$ModeTag._26

		    ELSE

			AND	r0, r0, #Mode_SVC_26
			CMP	r0, #Mode_SVC_26

		    ENDIF	
		ENDIF

		BEQ	NO_r14_test
ModeTag		SETS	""

		|
ModeTag		SETS ModeTag:CC:char
		]
List	  SETS List:RIGHT:(:LEN:List-1)		
	WEND

		CMP	r14, #VU14
		BEQ	$l.END

		LDR	r0,=VU14
		Report_Regs     "r14 incorrect - expected:__", r0, "__actual:__", r14
		B	$Error
	
NO_r14_test
$l.END
;~~~~~~~~~~
	LDR	r0, tmpr0$l

	LOCAL_END
	MEND

	; ---------------------------------------------------------------	
	MACRO
$L	Clear_System_CoProcessor_Regs
	; ---------------------------------------------------------------
	; 07/07/97 P Pearse - Use LOCAL
	; ------------------------------------------------
	LOCAL
	B	%F1

tmpr0$l	DCD 0
tmpr1$l	DCD 0

1
	STR	r0, tmpr0$l 
	STR	r1, tmpr1$l

	; ---------------------------------------------------------------
	; MMU disabled before other data changed 
	; - Use read/modify/write to avoid changing device dependent bits
	; ---------------------------------------------------------------
	MRC	CP_SYSTEM, 0, r0, CPSYS_Control, c0, 0	; Read
	; ---------------------------------------------------------------
	; Clear R & S
	; Disable alignment checking
	; Disable MMU
	; 
	; CAUTION - Assumes Endianness set correctly already
	; ---------------------------------------------------------------
	LDR	r1, =0xFFFFFCFC				; Mask device independent bits
							; - other than endianness 
	AND	r0, r0, r1				; Set  device independent bits
							; - other than endianness
	MCR	CP_SYSTEM, 0, r0, CPSYS_Control, c0, 0	; Write

	MOV	r0, #0
	MCR	CP_SYSTEM, 0, r0, CPSYS_Tran_TBL_Base, c0, 0
	MOV	r0, #0					; In case code moved/inserted
	MCR	CP_SYSTEM, 0, r0, CPSYS_Domain_Access, c0, 0


	MOV	r0, #0					
	MCR	CP_SYSTEM, 0, r0, CPSYS_Fault_Status , c0, 0	; Fault status bit 8 
								; ignored on write
	MOV	r0, #0					; In case code moved/inserted
	MCR	CP_SYSTEM, 0, r0, CPSYS_Fault_Address, c0, 0

	LDR	r1, tmpr1$l 
	LDR	r0, tmpr0$l
	LOCAL_END
	MEND

	; ---------------------------------------------------------------
	; Initialise banked registers, other than SYS
	; - SVC assumed used for re-establishing unknown mode on entry
	;   so r14 will get corrupted 
	; - allows for 26/32 bit addressing
	; - USR mode last since mode change NOT allowed from USR mode
	MACRO
$L	RegisterInit_AllModes $reg

	[	"$reg" /= "r0" :LAND: "$reg" /= "r1"
	! 0, "RegisterInit_AllModes: register should be r0 or r1"
	]
			GBLS	mRegUsed	; So RegisterCheck_AllModes uses same
mRegUsed	SETS	"$reg"

	; ---------------------------------------------------------------
	; IRQ - r13, r14
	; ---------------------------------------------------------------
   IF	{CONFIG} = 32
	MSR_M	CPSR, Mode_IRQ_32, $reg
   ELSE
	MSR_M	CPSR, Mode_IRQ_26, $reg
   ENDIF
	MOV	r13, #VI13
	MOV	r14, #VI14
	; ---------------------------------------------------------------
	; FIQ - r8 to r14
	; ---------------------------------------------------------------
   IF	{CONFIG} = 32
	MSR_M	CPSR, Mode_FIQ_32,$reg
   ELSE
	MSR_M	CPSR, Mode_FIQ_26,$reg
   ENDIF
	MOV	r8 , #VF8
	MOV	r9 , #VF9
	MOV	r10, #VF10
	MOV	r11, #VF11
	MOV	r12, #VF12
	MOV	r13, #VF13
	MOV	r14, #VF14
	; ---------------------------------------------------------------
	; ABT & UND 32 bit only, r13, r14
	; ---------------------------------------------------------------
   IF	{CONFIG} = 32
	MSR_M	CPSR, Mode_ABT_32,$reg
	MOV	r13, #VA13
	MOV	r14, #VA14

	MSR_M	CPSR, Mode_UND_32,$reg
	MOV	r13, #VN13
	MOV	r14, #VN14
   ELSE
	NOP	; MSR_M	CPSR, Mode_ABT_32 - see Test-Macros
	NOP	; 8 instructions
	NOP
	NOP
	NOP
	NOP
	NOP
	NOP
	NOP	; MOV	r13, #VA13
	NOP	; MOV	r14, #VA14

	NOP	; MSR_M	CPSR, Mode_UND_32 - see Test-Macros
	NOP	; 8 instructions
	NOP
	NOP
	NOP
	NOP
	NOP
	NOP
	NOP	; MOV	r13, #VN13
	NOP	; MOV	r14, #VN14
   ENDIF
	; ---------------------------------------------------------------
	; SVC - r13 only - see macro header
	; ---------------------------------------------------------------
   IF	{CONFIG} = 32
	MSR_M	CPSR, Mode_SVC_32,$reg
   ELSE
	MSR_M	CPSR, Mode_SVC_26,$reg
   ENDIF
	MOV	r13, #VS13
	; ---------------------------------------------------------------
	; USR	r0 - r14
	; ---------------------------------------------------------------
   IF	{CONFIG} = 32
	MSR_M	CPSR, Mode_USR_32,$reg
   ELSE
	MSR_M	CPSR, Mode_USR_26,$reg
   ENDIF
	RegisterInit	"$All_Registers"

	MEND

	; ---------------------------------------------------------------
	; Check banked registers against values set in RegisterInit_AllModes
	; - enters from unknown mode
	; - SVC assumed used for mode recovery, corrupts r14
	; - USR last since NO mode switch allowed
	MACRO
$L	RegisterCheck_AllModes	$Error, $reg
	; ---------------------------------------------------------------

	[ "$reg" /= "r0" :LAND: "$reg" /= "r1"
	! 0, "RegisterCheck_AllModes: register should be r0 or r1"
	]

	[	"$reg" /= "$mRegUsed"
	! 0, "RegisterCheck_AllModes: register should be as used by RegisterInit_AllModes"
	]

	B		$L.PastStore
$L.temp	DCD	0
$L.PastStore
;~~~~~~~~
	STR		$reg, $L.temp
	; ---------------------------------------------------------------
	; IRQ - r13, r14
	; ---------------------------------------------------------------
   IF	{CONFIG} = 32
	MSR_M	CPSR, Mode_IRQ_32, $reg
   ELSE
	MSR_M	CPSR, Mode_IRQ_26, $reg
   ENDIF
	CMP	r13, #VI13
	BNE	$Error
	CMP	r14, #VI14
	BNE	$Error
	; ---------------------------------------------------------------
	; FIQ - r8 to r14
	; ---------------------------------------------------------------
   IF	{CONFIG} = 32
	MSR_M	CPSR, Mode_FIQ_32, $reg
   ELSE
	MSR_M	CPSR, Mode_FIQ_26, $reg
   ENDIF
	CMP	r8 , #VF8
	BNE	$Error
	CMP	r9 , #VF9
	BNE	$Error
	CMP	r10, #VF10
	BNE	$Error
	CMP	r11, #VF11
	BNE	$Error
	CMP	r12, #VF12
	BNE	$Error
	CMP	r13, #VF13
	BNE	$Error
	CMP	r14, #VF14
	BNE	$Error
	; ---------------------------------------------------------------
	; ABT & UND 32 bit only, r13, r14
	; ---------------------------------------------------------------
   IF	{CONFIG} = 32
	MSR_M	CPSR, Mode_ABT_32, $reg
	CMP	r13, #VA13
	BNE	$Error
	CMP	r14, #VA14
	BNE	$Error

	MSR_M	CPSR, Mode_UND_32, $reg
	CMP	r13, #VN13
	BNE	$Error
	CMP	r14, #VN14
	BNE	$Error
   ELSE
	NOP	; MSR_M	CPSR, Mode_ABT_32 - see Test-Macros
	NOP	; 8 instructions
	NOP
	NOP
	NOP
	NOP
	NOP
	NOP
	NOP	; CMP	r13, #VA13
	NOP	; BNE	$Error
	NOP	; CMP	r14, #VA14
	NOP	; BNE	$Error

	NOP	; MSR_M	CPSR, Mode_UND_32 - see Test-Macros
	NOP	; 8 instructions
	NOP
	NOP
	NOP
	NOP
	NOP
	NOP
	NOP	; CMP	r13, #VN13
	NOP	; BNE	$Error
	NOP	; CMP	r14, #VN14
	NOP	; BNE	$Error
   ENDIF
	; ---------------------------------------------------------------
	; SVC - r13 only - see macro header
	; ---------------------------------------------------------------
   IF	{CONFIG} = 32
	MSR_M	CPSR, Mode_SVC_32, $reg
   ELSE
	MSR_M	CPSR, Mode_SVC_26, $reg
   ENDIF

	CMP r13, #VS13
	BNE	$Error

	; ---------------------------------------------------------------
	; SYS	r0 - r14, excluding register used for mode checking 
	; (tested in case mode switching thru SYS has deleterious effect)
	; ---------------------------------------------------------------

	[ ARM_ARCH >= 4
	MSR_M	CPSR, Mode_SYS_32, $reg

	[	"$reg" = "r0"
	RegisterCheck	$Error, "1,2,3,4,5,6,7,8,9,10,11,12,13,14"
	|
	RegisterCheck	$Error, "0,2,3,4,5,6,7,8,9,10,11,12,13,14"
	]

	]

	; ---------------------------------------------------------------
	; USR	r0 - r14
	; ---------------------------------------------------------------
   IF	{CONFIG} = 32
	MSR_M	CPSR, Mode_USR_32, $reg
   ELSE
	MSR_M	CPSR, Mode_USR_26, $reg
   ENDIF

	ADRL	$reg,$L.temp
	LDR	$reg,[$reg]

	RegisterCheck	$Error, "$All_Registers"

	MEND

;===========================================================
; BST command macros
;
; Notes:
; ------
; - comments included for display if BST trace on
; - RETVAL maintained for individual instructions so MACROS
;   can be defined
;   - since the SCAN_N, INTEST calls may occur on entry to debug
;     or on return to debug the pc is incremented by the minimum
;     common amount i.e. 12 bytes, rather than the maximum amount
;     (occurring on entry to debug) of 16 bytes
; - Allow re-location of variables by defining op-code variables and adding
;   actual values/offsets e.g. use of SUBVAL, MOVVAL below
; - Revision 1 will have 'BYPASS' replaced with 'RESTART'

;===========================================================

;		MACRO
;		Define_Bst_Constants
; SC_Embedded_ICE			EQU	2
; SC_Data_Plus_BREAKPOINT		EQU	1
;		MEND

	; ------------------------------------------------
	; Debug speed NOP instruction
	; - RETVAL always += PCIncrement
	; - BREAKPT set as passed - affects speed of NEXT instruction
	; ------------------------------------------------
	; 23/05/97 P Pearse : THUMB part to generic
	; ------------------------------------------------
    
		MACRO
		Bst_NOP	$BREAKPT
		[	"$BREAKPT" /= "S" :LAND: "$BREAKPT" /= "D"
		!	1, "Bst_NOP takes S or D - NOT $BREAKPT"
		MEXIT
		]
		[	"$BREAKPT" = "S" :LAND: VARIANT = "ARM9"
		!	1, "\n\tPANIC: Bst_NOP S with device ARM9TD, probably won't work"
		MEXIT
		]
		[	PCIncrement = 2
		BST	"THUMBINST_$BREAKPT NOP"
		|
		BST	"ARMINST_$BREAKPT NOP"
		]
RETVAL		SETA	RETVAL + PCIncrement			
		MEND

	; ------------------------------------------------
	; Sets current scan chain into test mode
	; ------------------------------------------------
	; 07/07/97 P Pearse - REVAL increment for testing
	; ------------------------------------------------  
		MACRO
		Bst_Intest
		DCB	"INTEST\n"

		[ :DEF: PMPtest
		[ PMPtest = {TRUE}
		! 0, "PMPtest: RETVAL + pipelength increments"
RETVAL		SETA	RETVAL + $PipelineLen * PCIncrement
		]
		]

		MEND

	; ------------------------------------------------
	; Set scan chain reg of embedded ICE to passed value
	; P Pearse 27/06/97 : Check for reserved chains
	; ------------------------------------------------

		MACRO
		Bst_Set_Scan_Chain $chain
		[	"$chain" = ""
		!	1, "Incorrect use of Debug-Macros: Bst_Set_Scan_Chain"
		!	1, "Missing parameter"
		MEXIT
		]
		DCB	"SCAN_N $chain\n"	; Set scan chain $chain
		MEND

	; ----------------------------------------
	; read dbg_status and check T bit set
	; DBG_STATUS appears on the bottom 5 bits of the scanned out data
	; For 38 bits supply 10 bytes
	; - currently pattern = (b)00..r/w bit[0 = read] ..Address bits....reg bits
	;   see ARM7TDMI Data sheet 9.2.1 and 9.6
	; -----------------------------------------
	
		MACRO
		Bst_Check_TBit_Set
		DCB	"ICEBINST READ DBG_STATUS ; Data to scan chain\n"
		DCB	"ICEBINST READ DBG_STATUS ; Provide data to clock out DBG_STATUS\n"
		DCB	"GET 1	  ; get 38 bit TDO into var 1\n"		; Suck the data off the data bus.
; 		DCB	"IFMASK 1 0000000010 FFFFFFFFEF	; check Tbit set\n"	; Complain if Tbit isn't set.
		MEND

	; ----------------------------------------
	; read dbg_status and check T bit clear
	; -----------------------------------------
	; 29/09/97 P Pearse Added
	; -----------------------------------------	
		MACRO
		Bst_Check_TBit_Clear
		DCB	"ICEBINST READ DBG_STATUS ; Data to scan chain\n"
		DCB	"ICEBINST READ DBG_STATUS ; Provide data to clock out DBG_STATUS\n"
		DCB	"GET 1	  ; get 38 bit TDO into var 1\n"		; Suck the data off the data bus.
; 		DCB	"IFMASK 1 0000000000 FFFFFFFFEF	; check Tbit set\n"	; Complain if Tbit isn't set.
		MEND
	; -----------------------------------------------
	; Run pipelined instructions
	; - if full speed instructions are Load/Store then core
	;   returns to Debug Mode
	; - otherwise (full speed instruction and NON Load/Store instruction) 
	;   the core will re-synchronise to MCLK and NOT re-enter Debug Mode
	; ------------------------------------------------
	; 07/07/97 P Pearse - Print REVAL for testing
	; ------------------------------------------------  
  
		MACRO
		Bst_Run
		DCB	"RESTART\n"
		DCB	"EXIT\n"

		[ :DEF: PMPtest
		[ PMPtest = {TRUE}
		! 0, "RETVAL is $RETVAL "
		]
		]
		
		MEND

	; ------------------------------------------------
	; Return from debug mode by subtracting stored count from PC
	;
	; - checks stored count within range
	; - adds 4 for the sub itself
	; - adds an extra 4 for the incorrect addition on entry 
	;   (12 NOT 16 - see notes above)
	; - adjust for sub to use ror/imm form if necessary
	; - preceding instruction must set BREAKPT to 'run at system speed'
	; - because instruction is NOT load/store the core will now 
	;   re-synchronise to MCLK and NOT re-enter Debug Mode
	; 
	; ------------------------------------------------
	; 23/05/97 P Pearse : THUMB part adjusted to match logs
	; 29/05/97 P Pearse : Adjust for ARM710T started via DBRQ
	;		      - this way such that unconverted files may still
	;			use the ICEinit method
	;		      - ** REMOVE once all original files (including THUMB)
	;			   have been converted
	; 30/05	   P Pearse : NOT necessary
	; ------------------------------------------------

		MACRO
		Bst_Return
		[	PCIncrement = 2

	; ---------------------------
	; Return from THUMB
	; ---------------------------
	; 
	; Setup return branch
	; 0xE000 == unconditional branch 
	; - bits 10 to 0 are (signed offset)/2 to PC
	; - PC value offset will be applied to is
	;   PC @ Branch instr + 4 - See Ref Manual: Thumb Instructions
	; - PC here is RETVAL + Return Address
	;   so PC to be used will be RETVAL + Return Address + 4
	;   so offset required