initialize.c

visual dsp++ audio iir

#include "Talkthrough.h"

//--------------------------------------------------------------------------//
// Function:	Init_EBIU													//
//																			//
// Description:	This function initializes and enables asynchronous memory 	//
//				banks in External Bus Interface Unit so that Flash A can be //
//				accessed.													//
//--------------------------------------------------------------------------//
void Init_EBIU(void)
{
	*pEBIU_AMBCTL0	= 0x7bb07bb0;  //需要在此填入控制时序//
	*pEBIU_AMBCTL1	= 0x7bb07bb0;  //需要在此填入控制时序//
	*pEBIU_AMGCTL	= 0x000f;  //需要在此填入使能控制//
}


//--------------------------------------------------------------------------//
// Function:	Init_Flash													//
//																			//
// Description:	This function initializes pin direction of Port A in Flash A//
//				to output.  The AD1836_RESET on the ADSP-BF533 EZ-KIT board //
//				is connected to Port A.										//
//--------------------------------------------------------------------------//
void Init_Flash(void)
{
	*pFlashA_PortA_Dir = 0x1;
}


//--------------------------------------------------------------------------//
// Function:	Init1836()													//
//																			//
// Description:	This function sets up the SPI port to configure the AD1836. //
//				The content of the array sCodec1836TxRegs is sent to the 	//
//				codec.														//
//--------------------------------------------------------------------------//
void Init1836(void)
{
	int i;
	int j;
	static unsigned char ucActive_LED = 0x01;
	
	// write to Port A to reset AD1836
	*pFlashA_PortA_Data = 0x00;
	
	// write to Port A to enable AD1836
	*pFlashA_PortA_Data = ucActive_LED;
	
	// wait to recover from reset
	for (i=0; i<0xf000; i++);

	// Enable PF4
	*pSPI_FLG = FLS4;
	// Set baud rate SCK = HCLK/(2*SPIBAUD) SCK = 2MHz	
	*pSPI_BAUD = 16;
	// configure spi port
	// SPI DMA write, 16-bit data, MSB first, SPI Master
	*pSPI_CTL = TIMOD_DMA_TX | SIZE | MSTR;
	
	// Set up DMA5 to transmit
	// Map DMA5 to SPI
	*pDMA5_PERIPHERAL_MAP	= 0x5000;
	
	// Configure DMA5
	// 16-bit transfers
	*pDMA5_CONFIG = WDSIZE_16;
	// Start address of data buffer
	*pDMA5_START_ADDR = (void *) sCodec1836TxRegs;
	// DMA inner loop count
	*pDMA5_X_COUNT = CODEC_1836_REGS_LENGTH;
	// Inner loop address increment
	*pDMA5_X_MODIFY = 2;
	
	// enable DMAs
	*pDMA5_CONFIG = (*pDMA5_CONFIG | DMAEN);
	// enable spi
	*pSPI_CTL = (*pSPI_CTL | SPE);
	
	// wait until dma transfers for spi are finished 
	for (j=0; j<0xaff; j++);
	
	// disable spi
	*pSPI_CTL = 0x0000;
}


//--------------------------------------------------------------------------//
// Function:	Init_Sport0													//
//																			//
// Description:	Configure Sport0 for TDM mode, to transmit/receive data 	//
//				to/from the AD1836. Configure Sport for external clocks and //
//				frame syncs.												//
//--------------------------------------------------------------------------//
void Init_Sport0(void)
{
	// Sport0 receive configuration
	// External CLK, External Frame sync, MSB first
	// 16-bit data
	*pSPORT0_RCR1 = RFSR|RCKFE;
	*pSPORT0_RCR2 = SLEN_16|RSFSE;
		
	// Sport0 transmit configuration
	// External CLK, External Frame sync, MSB first
	// 16-bit data
	*pSPORT0_TCR1 = TFSR|TCKFE;
	*pSPORT0_TCR2 = SLEN_16|TSFSE;
}


//--------------------------------------------------------------------------//
// Function:	Init_DMA													//
//																			//
// Description:	Initialize DMA1 in autobuffer mode to receive and DMA2 in	//
//				autobuffer mode to transmit									//
//--------------------------------------------------------------------------//
void Init_DMA(void)
{
	pDmaDescR0.next_desc_ptr = (unsigned int)(&pDmaDescR1);
	pDmaDescR0.start_addr =  (unsigned long)iRxBuffer0;
	pDmaDescR0.cfg = DMAFLOW | NDSIZE | WDSIZE_16 | WNR| DMAEN| DI_EN ;
	pDmaDescR0.x_count = 2*VEC_SIZE;
	pDmaDescR0.x_modify = 2;
	pDmaDescR0.y_count = 0;
	pDmaDescR0.y_modify = 0;
	
	pDmaDescR1.next_desc_ptr = (unsigned int)(&pDmaDescR0);
	pDmaDescR1.start_addr =  (unsigned long)iRxBuffer1;
	pDmaDescR1.cfg = DMAFLOW | NDSIZE | WDSIZE_16 | WNR| DMAEN| DI_EN ;
	pDmaDescR1.x_count = 2*VEC_SIZE;
	pDmaDescR1.x_modify = 2;
	pDmaDescR1.y_count = 0;
	pDmaDescR1.y_modify = 0;
	
	pDmaDescT0.next_desc_ptr = (unsigned int)(&pDmaDescT1);
	pDmaDescT0.start_addr =  (unsigned long)iTxBuffer0;
	pDmaDescT0.cfg = DMAFLOW | NDSIZE | WDSIZE_16| DMAEN| DI_EN ;
	pDmaDescT0.x_count = 2*VEC_SIZE;
	pDmaDescT0.x_modify = 2;
	pDmaDescT0.y_count = 0;
	pDmaDescT0.y_modify = 0;
	
	pDmaDescT1.next_desc_ptr = (unsigned int)(&pDmaDescT0);
	pDmaDescT1.start_addr =  (unsigned long)iTxBuffer1;
	pDmaDescT1.cfg = DMAFLOW | NDSIZE | WDSIZE_16| DMAEN| DI_EN ;
	pDmaDescT1.x_count = 2*VEC_SIZE;
	pDmaDescT1.x_modify = 2;
	pDmaDescT1.y_count = 0;
	pDmaDescT1.y_modify = 0;
	
	// Set up DMA1 to receive
	// Map DMA1 to Sport0 RX
	*pDMA1_PERIPHERAL_MAP = 0x1000;   //需要填入控制//
	ssync();
	// Configure DMA1
	// 32-bit transfers, Interrupt on completion, Autobuffer mode
	*pDMA1_CONFIG = DMAFLOW | NDSIZE | WDSIZE_16 | WNR;
	*pDMA1_NEXT_DESC_PTR = 	&pDmaDescR0;
	// Start address of data buffer
	*pDMA1_START_ADDR = iRxBuffer0;
	// DMA inner loop count
	*pDMA1_X_COUNT = 0;
	// Inner loop address increment
	*pDMA1_X_MODIFY	= 0;
	
	
	// Set up DMA2 to transmit
	// Map DMA2 to Sport0 TX
	*pDMA2_PERIPHERAL_MAP = 0x2000;  //需要填入控制//
	ssync();
	// Configure DMA2
	// 32-bit transfers, Autobuffer mode
	*pDMA2_CONFIG = DMAFLOW | NDSIZE | WDSIZE_16;
	*pDMA2_NEXT_DESC_PTR = 	&pDmaDescT0;
	// Start address of data buffer
	*pDMA2_START_ADDR = iTxBuffer0;
	// DMA inner loop count
	*pDMA2_X_COUNT = 0;
	// Inner loop address increment
	*pDMA2_X_MODIFY	= 0;
}


//--------------------------------------------------------------------------//
// Function:	Init_Interrupts												//
//																			//
// Description:	Initialize Interrupt for Sport0 RX							//
//--------------------------------------------------------------------------//
void Init_Sport_Interrupts(void)
{
	// Set Sport0 RX (DMA1) interrupt priority to 2 = IVG9 
	*pSIC_IAR0 = 0xffffffff;
	*pSIC_IAR1 = 0xffffff2f;
	*pSIC_IAR2 = 0xffffffff;

	// assign ISRs to interrupt vectors
	// Sport0 RX ISR -> IVG 9
	register_handler(ik_ivg9, Sport0_RX_ISR);		

	// enable Sport0 RX interrupt
	*pSIC_IMASK = 0x00000200;
	ssync();
}


//--------------------------------------------------------------------------//
// Function:	Enable_DMA_Sport											//
//																			//
// Description:	Enable DMA1, DMA2, Sport0 TX and Sport0 RX					//
//--------------------------------------------------------------------------//
void Enable_DMA_Sport0(void)
{
	// enable DMAs
	*pDMA2_CONFIG	= (*pDMA2_CONFIG | DMAEN);
	*pDMA1_CONFIG	= (*pDMA1_CONFIG | DMAEN);
	
	// enable Sport0 TX and RX
	*pSPORT0_TCR1 	= (*pSPORT0_TCR1 | TSPEN);
	*pSPORT0_RCR1 	= (*pSPORT0_RCR1 | RSPEN);
}