📄 clock_timer_good.lst
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(0209)
(0210) IF ( AGND_BYPASS )
(0211) ;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
(0212) ; The 5V trim has already been set, but we need to update the AGNDBYP
(0213) ; bit in the write-only BDG_TR register. Recalculate the register
(0214) ; value using the proper trim values.
(0215) ;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
(0216) M8SSC_SetTableVoltageTrim 1, SSCTBL1_TRIM_BGR_5V, AGND_BYPASS_JUST
(0217) ENDIF
(0218) ELSE
(0219) ; 3.3V operation trim codes
(0220) ; Set the IMO and Bandgap trims for 3v operation
(0221) M8SSC_SetTableTrims 1, SSCTBL1_TRIM_IMO_3V_24MHZ, SSCTBL1_TRIM_BGR_3V, AGN_BYPASS_JUST
(0222)
(0223) ; Set the IMO Gain Trim for 3v operation
(0224) M8SSC_SetTableIMOGainTrim 2, SSCTBL2_TRIM_IMO_GAIN_3V
(0225)
(0226) ENDIF ; 3.3 Volt Operation
(0227)
(0228) mov [bSSC_KEY1], 0 ; Lock out Flash and Supervisiory operations
0078: 55 F8 00 MOV [248],0
(0229) mov [bSSC_KEYSP], 0
007B: 55 F9 00 MOV [249],0
(0230)
(0231) ;---------------------------------------
(0232) ; Initialize Crystal Oscillator and PLL
(0233) ;---------------------------------------
(0234)
(0235) ; Either no ECO, or waiting for stable clock is to be done in main
(0236) M8C_SetBank1
007E: 71 10 OR F,16
(0237) mov reg[OSC_CR0], (SLEEP_TIMER_JUST | OSC_CR0_CPU_12MHz)
0080: 62 E0 02 MOV REG[224],2
(0238) M8C_SetBank0
0083: 70 EF AND F,239
(0239) M8C_ClearWDTAndSleep ; Reset the watch dog
0085: 62 E3 38 MOV REG[227],56
(0240)
(0241) ;---------------------------------------------
(0242) ; Enter the Large Memory Model, if applicable
(0243) ;---------------------------------------------
(0244) IF ( SYSTEM_LARGE_MEMORY_MODEL )
(0245) RAM_SETPAGE_STK SYSTEM_STACK_PAGE ; relocate stack page ...
0088: 62 D1 03 MOV REG[209],3
(0246) mov A, SYSTEM_STACK_BASE_ADDR ; and offset, if any
008B: 50 00 MOV A,0
(0247) swap A, SP
008D: 4E SWAP SP,A
(0248) RAM_SETPAGE_IDX2STK ; initialize other page pointers
008E: 62 D3 03 MOV REG[211],3
(0249) RAM_SETPAGE_CUR 0
0091: 62 D0 00 MOV REG[208],0
(0250) RAM_SETPAGE_MVW 0
0094: 62 D5 00 MOV REG[213],0
(0251) RAM_SETPAGE_MVR 0
0097: 62 D4 00 MOV REG[212],0
(0252)
(0253) IF ( SYSTEM_IDXPG_TRACKS_STK_PP ); Now enable paging:
(0254) or F, FLAG_PGMODE_11b ; LMM w/ IndexPage<==>StackPage
009A: 71 C0 OR F,192
(0255) ELSE
(0256) or F, FLAG_PGMODE_10b ; LMM w/ independent IndexPage
(0257) ENDIF ; SYSTEM_IDXPG_TRACKS_STK_PP
(0258) ELSE
(0259) mov A, __ramareas_end ; Set top of stack to end of used RAM
(0260) swap SP, A
(0261) ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
(0262)
(0263) ;-------------------------
(0264) ; Load Base Configuration
(0265) ;-------------------------
(0266) ; Load global parameter settings and load the user modules in the
(0267) ; base configuration. Exceptions: (1) Leave CPU Speed fast as possible
(0268) ; to minimize start up time; (2) We may still need to play with the
(0269) ; Sleep Timer.
(0270) ;
(0271) lcall LoadConfigInit
009C: 7C 03 26 LCALL 0x0326
(0272) M8C_SetBank1
009F: 71 10 OR F,16
(0273) and reg[DEC_CR1], 0x3F
00A1: 41 E7 3F AND REG[231],63
(0274) or reg[DEC_CR1], 0x80
00A4: 43 E7 80 OR REG[231],128
(0275) M8C_SetBank0
00A7: 70 EF AND F,239
(0276) ;-----------------------------------
(0277) ; Initialize C Run-Time Environment
(0278) ;-----------------------------------
(0279) IF ( C_LANGUAGE_SUPPORT )
(0280) IF ( SYSTEM_SMALL_MEMORY_MODEL )
(0281) mov A,0 ; clear the 'bss' segment to zero
(0282) mov [__r0],<__bss_start
(0283) BssLoop:
(0284) cmp [__r0],<__bss_end
(0285) jz BssDone
(0286) mvi [__r0],A
(0287) jmp BssLoop
(0288) BssDone:
(0289) mov A,>__idata_start ; copy idata to data segment
(0290) mov X,<__idata_start
(0291) mov [__r0],<__data_start
(0292) IDataLoop:
(0293) cmp [__r0],<__data_end
(0294) jz C_RTE_Done
(0295) push A
(0296) romx
(0297) mvi [__r0],A
(0298) pop A
(0299) inc X
(0300) adc A,0
(0301) jmp IDataLoop
(0302)
(0303) ENDIF ; SYSTEM_SMALL_MEMORY_MODEL
(0304)
(0305) IF ( SYSTEM_LARGE_MEMORY_MODEL )
(0306) mov reg[CUR_PP], >__r0 ; force direct addr mode instructions
00A9: 62 D0 00 MOV REG[208],0
(0307) ; to use the Virtual Register page.
(0308)
(0309) ; Dereference the constant (flash) pointer pXIData to access the start
(0310) ; of the extended idata area, "xidata." Xidata follows the end of the
(0311) ; text segment and may have been relocated by the Code Compressor.
(0312) ;
(0313) mov A, >__pXIData ; Get the address of the flash
00AC: 50 01 MOV A,1
(0314) mov X, <__pXIData ; pointer to the xidata area.
00AE: 57 50 MOV X,80
(0315) push A
00B0: 08 PUSH A
(0316) romx ; get the MSB of xidata's address
00B1: 28 ROMX
(0317) mov [__r0], A
00B2: 53 1F MOV [__r0],A
(0318) pop A
00B4: 18 POP A
(0319) inc X
00B5: 75 INC X
(0320) adc A, 0
00B6: 09 00 ADC A,0
(0321) romx ; get the LSB of xidata's address
00B8: 28 ROMX
(0322) swap A, X
00B9: 4B SWAP A,X
(0323) mov A, [__r0] ; pXIData (in [A,X]) points to the
00BA: 51 1F MOV A,[31]
(0324) ; XIData structure list in flash
(0325) jmp .AccessStruct
00BC: 80 04 JMP 0x00C1
(0326)
(0327) ; Unpack one element in the xidata "structure list" that specifies the
(0328) ; values of C variables. Each structure contains 3 member elements.
(0329) ; The first is a pointer to a contiguous block of RAM to be initial-
(0330) ; ized. Blocks are always 255 bytes or less in length and never cross
(0331) ; RAM page boundaries. The list terminates when the MSB of the pointer
(0332) ; contains 0xFF. There are two formats for the struct depending on the
(0333) ; value in the second member element, an unsigned byte:
(0334) ; (1) If the value of the second element is non-zero, it represents
(0335) ; the 'size' of the block of RAM to be initialized. In this case, the
(0336) ; third member of the struct is an array of bytes of length 'size' and
(0337) ; the bytes are copied to the block of RAM.
(0338) ; (2) If the value of the second element is zero, the block of RAM is
(0339) ; to be cleared to zero. In this case, the third member of the struct
(0340) ; is an unsigned byte containing the number of bytes to clear.
(0341)
(0342) .AccessNextStructLoop:
(0343) inc X ; pXIData++
00BE: 75 INC X
(0344) adc A, 0
00BF: 09 00 ADC A,0
(0345) .AccessStruct: ; Entry point for first block
(0346) ;
(0347) ; Assert: pXIData in [A,X] points to the beginning of an XIData struct.
(0348) ;
(0349) M8C_ClearWDT ; Clear the watchdog for long inits
00C1: 62 E3 00 MOV REG[227],0
(0350) push A
00C4: 08 PUSH A
(0351) romx ; MSB of RAM addr (CPU.A <- *pXIData)
00C5: 28 ROMX
(0352) mov reg[MVW_PP], A ; for use with MVI write operations
00C6: 60 D5 MOV REG[213],A
(0353) inc A ; End of Struct List? (MSB==0xFF?)
00C8: 74 INC A
(0354) jz .C_RTE_WrapUp ; Yes, C runtime environment complete
00C9: A0 4B JZ 0x0115
(0355) pop A ; restore pXIData to [A,X]
00CB: 18 POP A
(0356) inc X ; pXIData++
00CC: 75 INC X
(0357) adc A, 0
00CD: 09 00 ADC A,0
(0358) push A
00CF: 08 PUSH A
(0359) romx ; LSB of RAM addr (CPU.A <- *pXIData)
00D0: 28 ROMX
(0360) mov [__r0], A ; RAM Addr now in [reg[MVW_PP],[__r0]]
00D1: 53 1F MOV [__r0],A
(0361) pop A ; restore pXIData to [A,X]
00D3: 18 POP A
(0362) inc X ; pXIData++ (point to size)
00D4: 75 INC X
(0363) adc A, 0
00D5: 09 00 ADC A,0
(0364) push A
00D7: 08 PUSH A
(0365) romx ; Get the size (CPU.A <- *pXIData)
00D8: 28 ROMX
(0366) jz .ClearRAMBlockToZero ; If Size==0, then go clear RAM
00D9: A0 1C JZ 0x00F6
(0367) mov [__r1], A ; else downcount in __r1
00DB: 53 1E MOV [__r1],A
(0368) pop A ; restore pXIData to [A,X]
00DD: 18 POP A
(0369)
(0370) .CopyNextByteLoop:
(0371) ; For each byte in the structure's array member, copy from flash to RAM.
(0372) ; Assert: pXIData in [A,X] points to previous byte of flash source;
(0373) ; [reg[MVW_PP],[__r0]] points to next RAM destination;
(0374) ; __r1 holds a non-zero count of the number of bytes remaining.
(0375) ;
(0376) inc X ; pXIData++ (point to next data byte)
00DE: 75 INC X
(0377) adc A, 0
00DF: 09 00 ADC A,0
(0378) push A
00E1: 08 PUSH A
(0379) romx ; Get the data value (CPU.A <- *pXIData)
00E2: 28 ROMX
(0380) mvi [__r0], A ; Transfer the data to RAM
00E3: 3F 1F MVI [__r0],A
(0381) tst [__r0], 0xff ; Check for page crossing
00E5: 47 1F FF TST [31],255
(0382) jnz .CopyLoopTail ; No crossing, keep going
00E8: B0 06 JNZ 0x00EF
(0383) mov A, reg[ MVW_PP] ; If crossing, bump MVW page reg
00EA: 5D D5 MOV A,REG[213]
(0384) inc A
00EC: 74 INC A
(0385) mov reg[ MVW_PP], A
00ED: 60 D5 MOV REG[213],A
(0386) .CopyLoopTail:
(0387) pop A ; restore pXIData to [A,X]
00EF: 18 POP A
(0388) dec [__r1] ; End of this array in flash?
00F0: 7A 1E DEC [__r1]
(0389) jnz .CopyNextByteLoop ; No, more bytes to copy
00F2: BF EB JNZ 0x00DE
(0390) jmp .AccessNextStructLoop ; Yes, initialize another RAM block
00F4: 8F C9 JMP 0x00BE
(0391)
(0392) .ClearRAMBlockToZero:
(0393) pop A ; restore pXIData to [A,X]
00F6: 18 POP A
(0394) inc X ; pXIData++ (point to next data byte)
00F7: 75 INC X
(0395) adc A, 0
00F8: 09 00 ADC A,0
(0396) push A
00FA: 08 PUSH A
(0397) romx ; Get the run length (CPU.A <- *pXIData)
00FB: 28 ROMX
(0398) mov [__r1], A ; Initialize downcounter
00FC: 53 1E MOV [__r1],A
(0399) mov A, 0 ; Initialize source data
00FE: 50 00 MOV A,0
(0400)
(0401) .ClearRAMBlockLoop:
(0402) ; Assert: [reg[MVW_PP],[__r0]] points to next RAM destination and
(0403) ; __r1 holds a non-zero count of the number of bytes remaining.
(0404) ;
(0405) mvi [__r0], A ; Clear a byte
0100: 3F 1F MVI [__r0],A
(0406) tst [__r0], 0xff ; Check for page crossing
0102: 47 1F FF TST [31],255
(0407) jnz .ClearLoopTail ; No crossing, keep going
0105: B0 08 JNZ 0x010E
(0408) mov A, reg[ MVW_PP] ; If crossing, bump MVW page reg
0107: 5D D5 MOV A,REG[213]
(0409) inc A
0109: 74 INC A
(0410) mov reg[ MVW_PP], A
010A: 60 D5 MOV REG[213],A
(0411) mov A, 0 ; Restore the zero used for clearing
010C: 50 00 MOV A,0
(0412) .ClearLoopTail:
(0413) dec [__r1] ; Was this the last byte?
010E: 7A 1E DEC [__r1]
(0414) jnz .ClearRAMBlockLoop ; No, continue
0110: BF EF JNZ 0x0100
(0415) pop A ; Yes, restore pXIData to [A,X] and
0112: 18 POP A
(0416) jmp .AccessNextStructLoop ; initialize another RAM block
0113: 8F AA JMP 0x00BE
(0417)
(0418) .C_RTE_WrapUp:
(0419) pop A ; balance stack
0115: 18 POP A
(0420)
(0421) ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
(0422)
(0423) C_RTE_Done:
(0424)
(0425) ENDIF ; C_LANGUAGE_SUPPORT
(0426)
(0427)
(0428) ;-------------------------------
(0429) ; Set Power-On Reset (POR) Level
(0430) ;-------------------------------
(0431) M8C_SetBank1
0116: 71 10 OR F,16
(0432)
(0433) IF (POWER_SETTING & POWER_SET_3V3) ; 3.3V Operation?
(0434) or reg[VLT_CR], VLT_CR_POR_LOW ; Yes, change to midpoint trip
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