📄 boot.lis
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0000 ;---------------------------------------------------
0000 ; Analog PSoC block Registers
0000 ;
0000 ; Note: the following registers are mapped into
0000 ; both register bank 0 AND register bank 1.
0000 ;---------------------------------------------------
0000
0000 ; Continuous Time PSoC block Type B Row 0 Col 0
0070 ACB00CR3: equ 70h ; Control register 3 (RW)
0071 ACB00CR0: equ 71h ; Control register 0 (RW)
0072 ACB00CR1: equ 72h ; Control register 1 (RW)
0073 ACB00CR2: equ 73h ; Control register 2 (RW)
0000
0000 ; Continuous Time PSoC block Type B Row 0 Col 1
0074 ACB01CR3: equ 74h ; Control register 3 (RW)
0075 ACB01CR0: equ 75h ; Control register 0 (RW)
0076 ACB01CR1: equ 76h ; Control register 1 (RW)
0077 ACB01CR2: equ 77h ; Control register 2 (RW)
0000
0000 ; Switched Cap PSoC blockType C Row 1 Col 0
0080 ASC10CR0: equ 80h ; Control register 0 (RW)
0081 ASC10CR1: equ 81h ; Control register 1 (RW)
0082 ASC10CR2: equ 82h ; Control register 2 (RW)
0083 ASC10CR3: equ 83h ; Control register 3 (RW)
0000
0000 ; Switched Cap PSoC blockType D Row 1 Col 1
0084 ASD11CR0: equ 84h ; Control register 0 (RW)
0085 ASD11CR1: equ 85h ; Control register 1 (RW)
0086 ASD11CR2: equ 86h ; Control register 2 (RW)
0087 ASD11CR3: equ 87h ; Control register 3 (RW)
0000
0000 ; Switched Cap PSoC blockType D Row 2 Col 0
0090 ASD20CR0: equ 90h ; Control register 0 (RW)
0091 ASD20CR1: equ 91h ; Control register 1 (RW)
0092 ASD20CR2: equ 92h ; Control register 2 (RW)
0093 ASD20CR3: equ 93h ; Control register 3 (RW)
0000
0000 ; Switched Cap PSoC blockType C Row 2 Col 1
0094 ASC21CR0: equ 94h ; Control register 0 (RW)
0095 ASC21CR1: equ 95h ; Control register 1 (RW)
0096 ASC21CR2: equ 96h ; Control register 2 (RW)
0097 ASC21CR3: equ 97h ; Control register 3 (RW)
0000
0000 ;------------------------------------------------
0000 ; Row Digital Interconnects
0000 ;
0000 ; Note: the following registers are mapped into
0000 ; both register bank 0 AND register bank 1.
0000 ;------------------------------------------------
0000
00B0 RDI0RI: equ B0h ; Row Digital Interconnect Row 0 Input Reg (RW)
00B1 RDI0SYN: equ B1h ; Row Digital Interconnect Row 0 Sync Reg (RW)
00B2 RDI0IS: equ B2h ; Row 0 Input Select Register (RW)
00B3 RDI0LT0: equ B3h ; Row 0 Look Up Table Register 0 (RW)
00B4 RDI0LT1: equ B4h ; Row 0 Look Up Table Register 1 (RW)
00B5 RDI0RO0: equ B5h ; Row 0 Output Register 0 (RW)
00B6 RDI0RO1: equ B6h ; Row 0 Output Register 1 (RW)
0000
0000 ;-----------------------------------------------
0000 ; Ram Page Pointers
0000 ;-----------------------------------------------
00D0 CUR_PP: equ D0h ; Current Page Pointer
00D1 STK_PP: equ D1h ; Stack Page Pointer
00D3 IDX_PP: equ D3h ; Index Page Pointer
00D4 MVR_PP: equ D4h ; MVI Read Page Pointer
00D5 MVW_PP: equ D5h ; MVI Write Page Pointer
0000
0000 ;------------------------------------------------
0000 ; I2C Configuration Registers
0000 ;------------------------------------------------
00D6 I2C_CFG: equ D6h ; I2C Configuration Register (RW)
0040 I2C_CFG_PINSEL: equ 40h ; MASK: Select P1[0] and P1[1] for I2C
0020 I2C_CFG_BUSERR_IE: equ 20h ; MASK: Enable interrupt on Bus Error
0010 I2C_CFG_STOP_IE: equ 10h ; MASK: Enable interrupt on Stop
0000 I2C_CFG_CLK_RATE_100K: equ 00h ; MASK: I2C clock set at 100K
0004 I2C_CFG_CLK_RATE_400K: equ 04h ; MASK: I2C clock set at 400K
0008 I2C_CFG_CLK_RATE_50K: equ 08h ; MASK: I2C clock set at 50K
000C I2C_CFG_CLK_RATE_1M6: equ 0Ch ; MASK: I2C clock set at 1.6M
000C I2C_CFG_CLK_RATE: equ 0Ch ; MASK: I2C clock rate setting mask
0002 I2C_CFG_PSELECT_MASTER: equ 02h ; MASK: Enable I2C Master
0001 I2C_CFG_PSELECT_SLAVE: equ 01h ; MASK: Enable I2C Slave
0000
00D7 I2C_SCR: equ D7h ; I2C Status and Control Register (#)
0080 I2C_SCR_BUSERR: equ 80h ; MASK: I2C Bus Error detected (RC)
0040 I2C_SCR_LOSTARB: equ 40h ; MASK: I2C Arbitration lost (RC)
0020 I2C_SCR_STOP: equ 20h ; MASK: I2C Stop detected (RC)
0010 I2C_SCR_ACK: equ 10h ; MASK: ACK the last byte (RW)
0008 I2C_SCR_ADDR: equ 08h ; MASK: Address rcv'd is Slave address (RC)
0004 I2C_SCR_XMIT: equ 04h ; MASK: Set transfer to tranmit mode (RW)
0002 I2C_SCR_LRB: equ 02h ; MASK: Last recieved bit (RC)
0001 I2C_SCR_BYTECOMPLETE: equ 01h ; MASK: Transfer of byte complete (RC)
0000
00D8 I2C_DR: equ D8h ; I2C Data Register (RW)
0000
00D9 I2C_MSCR: equ D9h ; I2C Master Status and Control Register (#)
0008 I2C_MSCR_BUSY: equ 08h ; MASK: I2C Busy (Start detected) (R)
0004 I2C_MSCR_MODE: equ 04h ; MASK: Start has been generated (R)
0002 I2C_MSCR_RESTART: equ 02h ; MASK: Generate a Restart condition (RW)
0001 I2C_MSCR_START: equ 01h ; MASK: Generate a Start condition (RW)
0000
0000 ;------------------------------------------------
0000 ; System and Global Resource Registers
0000 ;------------------------------------------------
00DA INT_CLR0: equ DAh ; Interrupt Clear Register 0 (RW)
0000 ; Use INT_MSK0 bit field masks
00DB INT_CLR1: equ DBh ; Interrupt Clear Register 1 (RW)
0000 ; Use INT_MSK1 bit field masks
00DC INT_CLR2: equ DCh ; Interrupt Clear Register 2 (RW)
0000 ; Use INT_MSK2 bit field masks
00DD INT_CLR3: equ DDh ; Interrupt Clear Register 3 (RW)
0000 ; Use INT_MSK3 bit field masks
0000
00DE INT_MSK3: equ DEh ; I2C and Software Mask Register (RW)
0080 INT_MSK3_ENSWINT: equ 80h ; MASK: enable/disable SW interrupt
0001 INT_MSK3_I2C: equ 01h ; MASK: enable/disable I2C interrupt
0000
00DF INT_MSK2: equ DFh ; USB Mask Register (RW)
0080 INT_MSK2_WAKEUP: equ 80h ; MASK: enable/disable I2C interrupt
0040 INT_MSK2_EP4: equ 40h ; MASK: enable/disable SW interrupt
0020 INT_MSK2_EP3: equ 20h ; MASK: enable/disable I2C interrupt
0010 INT_MSK2_EP2: equ 10h ; MASK: enable/disable SW interrupt
0008 INT_MSK2_EP1: equ 08h ; MASK: enable/disable I2C interrupt
0004 INT_MSK2_EP0: equ 04h ; MASK: enable/disable SW interrupt
0002 INT_MSK2_SOF: equ 02h ; MASK: enable/disable I2C interrupt
0001 INT_MSK2_BUS_RESET: equ 01h ; MASK: enable/disable SW interrupt
0000
00E0 INT_MSK0: equ E0h ; General Interrupt Mask Register (RW)
0080 INT_MSK0_VC3: equ 80h ; MASK: enable/disable VC3 interrupt
0040 INT_MSK0_SLEEP: equ 40h ; MASK: enable/disable sleep interrupt
0020 INT_MSK0_GPIO: equ 20h ; MASK: enable/disable GPIO interrupt
0004 INT_MSK0_ACOLUMN_1: equ 04h ; MASK: enable/disable Analog col 1 interrupt
0002 INT_MSK0_ACOLUMN_0: equ 02h ; MASK: enable/disable Analog col 0 interrupt
0001 INT_MSK0_VOLTAGE_MONITOR: equ 01h ; MASK: enable/disable Volts interrupt
0000
00E1 INT_MSK1: equ E1h ; Digital PSoC block Mask Register (RW)
0008 INT_MSK1_DCB03: equ 08h ; MASK: enable/disable DCB03 block interrupt
0004 INT_MSK1_DCB02: equ 04h ; MASK: enable/disable DCB02 block interrupt
0002 INT_MSK1_DBB01: equ 02h ; MASK: enable/disable DBB01 block interrupt
0001 INT_MSK1_DBB00: equ 01h ; MASK: enable/disable DBB00 block interrupt
0000
00E2 INT_VC: equ E2h ; Interrupt vector register (RC)
00E3 RES_WDT: equ E3h ; Watch Dog Timer Register (W)
0000
0000 ; DECIMATOR Control Registers
00E4 DEC_DH: equ E4h ; Data High Register (RW)
00E5 DEC_DL: equ E5h ; Data Low Register (RW)
00E6 DEC_CR0: equ E6h ; Data Control Register 0 (RW)
00E7 DEC_CR1: equ E7h ; Data Control Register 1 (RW)
0000
0000 ;------------------------------------------------------
0000 ; MAC Registers
0000 ;------------------------------------------------------
0000
00E8 MUL0_X: equ E8h ; Multiply Input X Register (W)
00E9 MUL0_Y: equ E9h ; Multiply Input Y Register (W)
00EA MUL0_DH: equ EAh ; Multiply Result High Byte Register (R)
00EB MUL0_DL: equ EBh ; Multiply Result Low Byte Register (R)
0000
00EC ACC0_DR1: equ ECh ; Accumulator Data Register 1 (RW)
00ED ACC0_DR0: equ EDh ; Accumulator Data Register 0 (RW)
00EE ACC0_DR3: equ EEh ; Accumulator Data Register 3 (RW)
00EF ACC0_DR2: equ EFh ; Accumulator Data Register 2 (RW)
0000
0000 ;------------------------------------------------------
0000 ; System Status and Control Registers
0000 ;
0000 ; Note: The following registers are mapped into both
0000 ; register bank 0 AND register bank 1.
0000 ;------------------------------------------------------
00F7 CPU_F: equ F7h ; CPU Flag Register Access (RO)
0000 ; Use FLAG_ masks defined at top of file
0000
00FD DAC_D: equ FDh ; DAC Data Register (RW)
0000
00FE CPU_SCR1: equ FEh ; CPU Status and Control Register #1 (#)
0080 CPU_SCR1_IRESS: equ 80h ; MASK: flag, Internal Reset Status bit
0010 CPU_SCR1_SLIMO: equ 10h ; MASK: Slow IMO (internal main osc) enable
0008 CPU_SCR1_ECO_ALWD_WR: equ 08h ; MASK: flag, ECO allowed has been written
0004 CPU_SCR1_ECO_ALLOWED: equ 04h ; MASK: ECO allowed to be enabled
0001 CPU_SCR1_IRAMDIS: equ 01h ; MASK: Disable RAM initialization on WDR
0000
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