📄 boot.lis
字号:
0000 ; Generated by PSoC Designer ver 4.2 b1013 : 02 September, 2004
0000 ;
0000 ;@Id: boot.tpl#681 @
0000 ;=============================================================================
0000 ; FILENAME: boot.asm
0000 ; VERSION: 4.16
0000 ; DATE: 6 October 2005
0000 ;
0000 ; DESCRIPTION:
0000 ; M8C Boot Code for CY8C24x90 microcontroller devices.
0000 ;
0000 ; Copyright (C) Cypress Semiconductor 2000-2005. All rights reserved.
0000 ;
0000 ; NOTES:
0000 ; PSoC Designer's Device Editor uses a template file, BOOT.TPL, located in
0000 ; the project's root directory to create BOOT.ASM. Any changes made to
0000 ; BOOT.ASM will be overwritten every time the project is generated; therefore
0000 ; changes should be made to BOOT.TPL not BOOT.ASM. Care must be taken when
0000 ; modifying BOOT.TPL so that replacement strings (such as @PROJECT_NAME)
0000 ; are not accidentally modified.
0000 ;
0000 ;=============================================================================
0000
0000 CPU_CLOCK: equ 0h ;CPU clock value
0007 CPU_CLOCK_MASK: equ 7h ;CPU clock mask
0000 CPU_CLOCK_JUST: equ 0h ;CPU clock value justified
0000 SLEEP_TIMER: equ 0h ;Sleep Timer value
0018 SLEEP_TIMER_MASK: equ 18h ;Sleep Timer mask
0000 SLEEP_TIMER_JUST: equ 0h ;Sleep Timer value justified
0000 LVD_TBEN: equ 0 ; Low Voltage Throttle-back enable value
0008 LVD_TBEN_MASK: equ 8 ; Low Voltage Throttle-back enable mask
0000 LVD_TBEN_JUST: equ 0 ; Low Voltage Throttle-back enable justified
0007 TRIP_VOLTAGE: equ 7h ;Trip Voltage value
0007 TRIP_VOLTAGE_MASK: equ 7h ;Trip Voltage mask
0007 TRIP_VOLTAGE_JUST: equ 7h ;Trip Voltage justified
0000
0010 POWER_SETTING: equ 10h
0010 POWER_SET_5V0: equ 10h ; MASK for 5.0V operation, fast and slow
0010 POWER_SET_5V0_24MHZ: equ 10h ; Power Setting value for 5.0V fast
0008 POWER_SET_3V3: equ 08h ; MASK for 3.3V operation, fast and slow
0008 POWER_SET_3V3_24MHZ: equ 08h ; Power Setting value for 3.3V fast
0000
0000 COMM_RX_PRESENT: equ 0 ;1 = TRUE
0000 WATCHDOG_ENABLE: equ 0 ;Watchdog Enable 1 = Enable
0000
000B CLOCK_DIV_VC1: equ bh ;VC1 clock divider
00F0 CLOCK_DIV_VC1_MASK: equ f0h ;VC1 clock divider mask
00B0 CLOCK_DIV_VC1_JUST: equ b0h ;VC1 clock divider justified
0009 CLOCK_DIV_VC2: equ 9h ;VC2 clock divider
000F CLOCK_DIV_VC2_MASK: equ fh ;VC2 clock divider mask
0009 CLOCK_DIV_VC2_JUST: equ 9h ;VC2 clock divider justified
0002 CLOCK_INPUT_VC3: equ 2h ;VC3 clock source
0003 CLOCK_INPUT_VC3_MASK: equ 3h ;VC3 clock source mask
0002 CLOCK_INPUT_VC3_JUST: equ 2h ;VC3 clock source justified
0063 CLOCK_DIV_VC3: equ 63h ;VC3 clock divider
00FF CLOCK_DIV_VC3_MASK: equ ffh ;VC3 clock divider mask
0063 CLOCK_DIV_VC3_JUST: equ 63h ;VC3 clock divider justified
0000 ANALOG_BUFFER_PWR: equ 0h ;Analog buffer power level
0001 ANALOG_BUFFER_PWR_MASK: equ 1h ;Analog buffer power level mask
0000 ANALOG_BUFFER_PWR_JUST: equ 0h ;Analog buffer power level justified
0000 ANALOG_POWER: equ 0h ;Analog power control
0007 ANALOG_POWER_MASK: equ 7h ;Analog power control mask
0000 ANALOG_POWER_JUST: equ 0h ;Analog power control justified
0000 OP_AMP_BIAS: equ 0h ;Op amp bias level
0040 OP_AMP_BIAS_MASK: equ 40h ;Op amp bias level mask
0000 OP_AMP_BIAS_JUST: equ 0h ;Op amp bias level justified
0000 REF_MUX: equ 0h ;Ref mux setting
0038 REF_MUX_MASK: equ 38h ;Ref mux setting mask
0000 REF_MUX_JUST: equ 0h ;Ref mux setting justified
0000 AGND_BYPASS: equ 0h ;AGndBypass setting
0040 AGND_BYPASS_MASK: equ 40h ;AGndBypass setting mask
0000 AGND_BYPASS_JUST: equ 0h ;AGndBypass setting justified
0000 SYSCLK_SOURCE: equ (0h | 0h) ;SysClk Source setting
0006 SYSCLK_SOURCE_MASK: equ (4h | 2h) ;SysClk Source setting mask
0000 SYSCLK_SOURCE_JUST: equ (0h | 0h) ;SysClk Source setting justified
0000 SYSCLK_2_DISABLE: equ 0h ;SysClk*2 Disable setting
0001 SYSCLK_2_DISABLE_MASK: equ 1h ;SysClk*2 Disable setting mask
0000 SYSCLK_2_DISABLE_JUST: equ 0h ;SysClk*2 Disable setting justified
0000 ;
0000 ; register initial values
0000 ;
0000 ANALOG_IO_CONTROL: equ 0h ;Analog IO Control register (ABF_CR)
0000 PORT_0_GLOBAL_SELECT: equ 0h ;Port 0 global select register (PRT0GS)
0000 PORT_0_DRIVE_0: equ 0h ;Port 0 drive mode 0 register (PRT0DM0)
00FF PORT_0_DRIVE_1: equ ffh ;Port 0 drive mode 1 register (PRT0DM1)
00FF PORT_0_DRIVE_2: equ ffh ;Port 0 drive mode 2 register (PRT0DM2)
0000 PORT_0_INTENABLE: equ 0h ;Port 0 interrupt enable register (PRT0IE)
0000 PORT_0_INTCTRL_0: equ 0h ;Port 0 interrupt control 0 register (PRT0IC0)
0000 PORT_0_INTCTRL_1: equ 0h ;Port 0 interrupt control 1 register (PRT0IC1)
0000 PORT_1_GLOBAL_SELECT: equ 0h ;Port 1 global select register (PRT1GS)
0000 PORT_1_DRIVE_0: equ 0h ;Port 1 drive mode 0 register (PRT1DM0)
00FF PORT_1_DRIVE_1: equ ffh ;Port 1 drive mode 1 register (PRT1DM1)
00FF PORT_1_DRIVE_2: equ ffh ;Port 1 drive mode 2 register (PRT1DM2)
0000 PORT_1_INTENABLE: equ 0h ;Port 1 interrupt enable register (PRT1IE)
0000 PORT_1_INTCTRL_0: equ 0h ;Port 1 interrupt control 0 register (PRT1IC0)
0000 PORT_1_INTCTRL_1: equ 0h ;Port 1 interrupt control 1 register (PRT1IC1)
0000 PORT_2_GLOBAL_SELECT: equ 0h ;Port 2 global select register (PRT2GS)
0000 PORT_2_DRIVE_0: equ 0h ;Port 2 drive mode 0 register (PRT2DM0)
00FF PORT_2_DRIVE_1: equ ffh ;Port 2 drive mode 1 register (PRT2DM1)
00FF PORT_2_DRIVE_2: equ ffh ;Port 2 drive mode 2 register (PRT2DM2)
0000 PORT_2_INTENABLE: equ 0h ;Port 2 interrupt enable register (PRT2IE)
0000 PORT_2_INTCTRL_0: equ 0h ;Port 2 interrupt control 0 register (PRT2IC0)
0000 PORT_2_INTCTRL_1: equ 0h ;Port 2 interrupt control 1 register (PRT2IC1)
0000 PORT_3_GLOBAL_SELECT: equ 0h ;Port 3 global select register (PRT3GS)
00FF PORT_3_DRIVE_0: equ ffh ;Port 3 drive mode 0 register (PRT3DM0)
0000 PORT_3_DRIVE_1: equ 0h ;Port 3 drive mode 1 register (PRT3DM1)
0000 PORT_3_DRIVE_2: equ 0h ;Port 3 drive mode 2 register (PRT3DM2)
0000 PORT_3_INTENABLE: equ 0h ;Port 3 interrupt enable register (PRT3IE)
0000 PORT_3_INTCTRL_0: equ 0h ;Port 3 interrupt control 0 register (PRT3IC0)
0000 PORT_3_INTCTRL_1: equ 0h ;Port 3 interrupt control 1 register (PRT3IC1)
0000 PORT_4_GLOBAL_SELECT: equ 0h ;Port 4 global select register (PRT4GS)
000F PORT_4_DRIVE_0: equ fh ;Port 4 drive mode 0 register (PRT4DM0)
00F0 PORT_4_DRIVE_1: equ f0h ;Port 4 drive mode 1 register (PRT4DM1)
00F0 PORT_4_DRIVE_2: equ f0h ;Port 4 drive mode 2 register (PRT4DM2)
0000 PORT_4_INTENABLE: equ 0h ;Port 4 interrupt enable register (PRT4IE)
0000 PORT_4_INTCTRL_0: equ 0h ;Port 4 interrupt control 0 register (PRT4IC0)
0000 PORT_4_INTCTRL_1: equ 0h ;Port 4 interrupt control 1 register (PRT4IC1)
0000 PORT_5_GLOBAL_SELECT: equ 0h ;Port 5 global select register (PRT5GS)
0007 PORT_5_DRIVE_0: equ 7h ;Port 5 drive mode 0 register (PRT5DM0)
0008 PORT_5_DRIVE_1: equ 8h ;Port 5 drive mode 1 register (PRT5DM1)
0008 PORT_5_DRIVE_2: equ 8h ;Port 5 drive mode 2 register (PRT5DM2)
00F0 PORT_5_INTENABLE: equ f0h ;Port 5 interrupt enable register (PRT5IE)
00F0 PORT_5_INTCTRL_0: equ f0h ;Port 5 interrupt control 0 register (PRT5IC0)
0000 PORT_5_INTCTRL_1: equ 0h ;Port 5 interrupt control 1 register (PRT5IC1)
0000 PORT_7_GLOBAL_SELECT: equ 0h ;Port 7 global select register (PRT7GS)
0000 PORT_7_DRIVE_0: equ 0h ;Port 7 drive mode 0 register (PRT7DM0)
0081 PORT_7_DRIVE_1: equ 81h ;Port 7 drive mode 1 register (PRT7DM1)
0081 PORT_7_DRIVE_2: equ 81h ;Port 7 drive mode 2 register (PRT7DM2)
0000 PORT_7_INTENABLE: equ 0h ;Port 7 interrupt enable register (PRT7IE)
0000 PORT_7_INTCTRL_0: equ 0h ;Port 7 interrupt control 0 register (PRT7IC0)
0000 PORT_7_INTCTRL_1: equ 0h ;Port 7 interrupt control 1 register (PRT7IC1)
0000
0000 ; end of file GlobalParams.inc
00C0 FLAG_PGMODE_MASK: equ C0h ; Paging control for > 256 bytes of RAM
0000 FLAG_PGMODE_0: equ 00h ; Direct to Page 0, indexed to Page 0
0040 FLAG_PGMODE_1: equ 40h ; Direct to Page 0, indexed to STK_PP page
0080 FLAG_PGMODE_2: equ 80h ; Direct to CUR_PP page, indexed to IDX_PP page
00C0 FLAG_PGMODE_3: equ C0h ; Direct to CUR_PP page, indexed to STK_PP page
0000 FLAG_PGMODE_00b: equ 00h ; Same as PGMODE_0
0040 FLAG_PGMODE_01b: equ 40h ; Same as PGMODE_1
0080 FLAG_PGMODE_10b: equ 80h ; Same as PGMODE_2
00C0 FLAG_PGMODE_11b: equ C0h ; Same as PGMODE_3
0010 FLAG_XIO_MASK: equ 10h ; I/O Bank select for register space
0008 FLAG_SUPER: equ 08h ; Supervisor Mode
0004 FLAG_CARRY: equ 04h ; Carry Condition Flag
0002 FLAG_ZERO: equ 02h ; Zero Condition Flag
0001 FLAG_GLOBAL_IE: equ 01h ; Glogal Interrupt Enable
0000
0000
0000 ;;=============================================================================
0000 ;; Register Space, Bank 0
0000 ;;=============================================================================
0000
0000 ;------------------------------------------------
0000 ; Port Registers
0000 ; Note: Also see this address range in Bank 1.
0000 ;------------------------------------------------
0000 ; Port 0
0000 PRT0DR: equ 00h ; Port 0 Data Register (RW)
0001 PRT0IE: equ 01h ; Port 0 Interrupt Enable Register (RW)
0002 PRT0GS: equ 02h ; Port 0 Global Select Register (RW)
0003 PRT0DM2: equ 03h ; Port 0 Drive Mode 2 (RW)
0000 ; Port 1
0004 PRT1DR: equ 04h ; Port 1 Data Register (RW)
0005 PRT1IE: equ 05h ; Port 1 Interrupt Enable Register (RW)
0006 PRT1GS: equ 06h ; Port 1 Global Select Register (RW)
0007 PRT1DM2: equ 07h ; Port 1 Drive Mode 2 (RW)
0000 ; Port 2
0008 PRT2DR: equ 08h ; Port 2 Data Register (RW)
0009 PRT2IE: equ 09h ; Port 2 Interrupt Enable Register (RW)
000A PRT2GS: equ 0Ah ; Port 2 Global Select Register (RW)
000B PRT2DM2: equ 0Bh ; Port 2 Drive Mode 2 (RW)
0000 ; Port 3
000C PRT3DR: equ 0Ch ; Port 3 Data Register (RW)
000D PRT3IE: equ 0Dh ; Port 3 Interrupt Enable Register (RW)
000E PRT3GS: equ 0Eh ; Port 3 Global Select Register (RW)
000F PRT3DM2: equ 0Fh ; Port 3 Drive Mode 2 (RW)
0000 ; Port 4
0010 PRT4DR: equ 10h ; Port 4 Data Register (RW)
0011 PRT4IE: equ 11h ; Port 4 Interrupt Enable Register (RW)
0012 PRT4GS: equ 12h ; Port 4 Global Select Register (RW)
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