psocgpioint.h

cy8c24794单片机程序

/******************************************************************************
*  Generated by PSoC Designer ver 4.2  b1013 : 02 September, 2004
******************************************************************************/
/*
*   PSoCGPIOINT.h
*   Data: 04 June, 2002
*   Copyright Cypress MicroSystems 2002
*
*  This file is generated by the Device Editor on Application Generation.
*  It contains equates that are useful in writing code relating to GPIO
*  related values.
*  
*  DO NOT EDIT THIS FILE MANUALLY, AS IT IS OVERWRITTEN!!!
*  Edits to this file will not be preserved.
*/
#include <m8c.h>
// Port_5_7 address and mask defines
#pragma	ioport	Port_5_7_Data_ADDR:	0x14
BYTE			Port_5_7_Data_ADDR;
#pragma	ioport	Port_5_7_DriveMode_0_ADDR:	0x114
BYTE			Port_5_7_DriveMode_0_ADDR;
#pragma	ioport	Port_5_7_DriveMode_1_ADDR:	0x115
BYTE			Port_5_7_DriveMode_1_ADDR;
#pragma	ioport	Port_5_7_DriveMode_2_ADDR:	0x17
BYTE			Port_5_7_DriveMode_2_ADDR;
#pragma	ioport	Port_5_7_GlobalSelect_ADDR:	0x16
BYTE			Port_5_7_GlobalSelect_ADDR;
#pragma	ioport	Port_5_7_IntCtrl_0_ADDR:	0x116
BYTE			Port_5_7_IntCtrl_0_ADDR;
#pragma	ioport	Port_5_7_IntCtrl_1_ADDR:	0x117
BYTE			Port_5_7_IntCtrl_1_ADDR;
#pragma	ioport	Port_5_7_IntEn_ADDR:	0x17
BYTE			Port_5_7_IntEn_ADDR;
#define Port_5_7_MASK 0x80
#pragma	ioport	Port_5_7_MUXBusCtrl_ADDR:	0x1ed
BYTE			Port_5_7_MUXBusCtrl_ADDR;
// Port_5_5 address and mask defines
#pragma	ioport	Port_5_5_Data_ADDR:	0x14
BYTE			Port_5_5_Data_ADDR;
#pragma	ioport	Port_5_5_DriveMode_0_ADDR:	0x114
BYTE			Port_5_5_DriveMode_0_ADDR;
#pragma	ioport	Port_5_5_DriveMode_1_ADDR:	0x115
BYTE			Port_5_5_DriveMode_1_ADDR;
#pragma	ioport	Port_5_5_DriveMode_2_ADDR:	0x17
BYTE			Port_5_5_DriveMode_2_ADDR;
#pragma	ioport	Port_5_5_GlobalSelect_ADDR:	0x16
BYTE			Port_5_5_GlobalSelect_ADDR;
#pragma	ioport	Port_5_5_IntCtrl_0_ADDR:	0x116
BYTE			Port_5_5_IntCtrl_0_ADDR;
#pragma	ioport	Port_5_5_IntCtrl_1_ADDR:	0x117
BYTE			Port_5_5_IntCtrl_1_ADDR;
#pragma	ioport	Port_5_5_IntEn_ADDR:	0x17
BYTE			Port_5_5_IntEn_ADDR;
#define Port_5_5_MASK 0x20
#pragma	ioport	Port_5_5_MUXBusCtrl_ADDR:	0x1ed
BYTE			Port_5_5_MUXBusCtrl_ADDR;
// Port_5_4 address and mask defines
#pragma	ioport	Port_5_4_Data_ADDR:	0x14
BYTE			Port_5_4_Data_ADDR;
#pragma	ioport	Port_5_4_DriveMode_0_ADDR:	0x114
BYTE			Port_5_4_DriveMode_0_ADDR;
#pragma	ioport	Port_5_4_DriveMode_1_ADDR:	0x115
BYTE			Port_5_4_DriveMode_1_ADDR;
#pragma	ioport	Port_5_4_DriveMode_2_ADDR:	0x17
BYTE			Port_5_4_DriveMode_2_ADDR;
#pragma	ioport	Port_5_4_GlobalSelect_ADDR:	0x16
BYTE			Port_5_4_GlobalSelect_ADDR;
#pragma	ioport	Port_5_4_IntCtrl_0_ADDR:	0x116
BYTE			Port_5_4_IntCtrl_0_ADDR;
#pragma	ioport	Port_5_4_IntCtrl_1_ADDR:	0x117
BYTE			Port_5_4_IntCtrl_1_ADDR;
#pragma	ioport	Port_5_4_IntEn_ADDR:	0x17
BYTE			Port_5_4_IntEn_ADDR;
#define Port_5_4_MASK 0x10
#pragma	ioport	Port_5_4_MUXBusCtrl_ADDR:	0x1ed
BYTE			Port_5_4_MUXBusCtrl_ADDR;
// Port_5_6 address and mask defines
#pragma	ioport	Port_5_6_Data_ADDR:	0x14
BYTE			Port_5_6_Data_ADDR;
#pragma	ioport	Port_5_6_DriveMode_0_ADDR:	0x114
BYTE			Port_5_6_DriveMode_0_ADDR;
#pragma	ioport	Port_5_6_DriveMode_1_ADDR:	0x115
BYTE			Port_5_6_DriveMode_1_ADDR;
#pragma	ioport	Port_5_6_DriveMode_2_ADDR:	0x17
BYTE			Port_5_6_DriveMode_2_ADDR;
#pragma	ioport	Port_5_6_GlobalSelect_ADDR:	0x16
BYTE			Port_5_6_GlobalSelect_ADDR;
#pragma	ioport	Port_5_6_IntCtrl_0_ADDR:	0x116
BYTE			Port_5_6_IntCtrl_0_ADDR;
#pragma	ioport	Port_5_6_IntCtrl_1_ADDR:	0x117
BYTE			Port_5_6_IntCtrl_1_ADDR;
#pragma	ioport	Port_5_6_IntEn_ADDR:	0x17
BYTE			Port_5_6_IntEn_ADDR;
#define Port_5_6_MASK 0x40
#pragma	ioport	Port_5_6_MUXBusCtrl_ADDR:	0x1ed
BYTE			Port_5_6_MUXBusCtrl_ADDR;