📄 main.c
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if(!(*pSPORT1_RCR1 & RSPEN)) {
opcode_addr = opcode;
// update descriptors
spi_se = &spi_se_desc;
spi_se->MOSI_regs_addr.START_ADDR_L = ((u32)&opcode_addr & 0xFFFF);
spi_se->MOSI_regs_addr.START_ADDR_H = (((u32)&opcode_addr >> 16) & 0xFFFF);
spi_se->MOSI_regs_value.START_ADDR_L = ((u32)addr & 0xFFFF);
spi_se->MOSI_regs_value.START_ADDR_H = (((u32)addr >> 16) & 0xFFFF);
// now DMA
*pDMA6_CONFIG = 0x0;
*pDMA6_PERIPHERAL_MAP = 0x6000;
*pDMA6_CURR_DESC_PTR = (void *)&(spi_se->MOSI_regs_addr);
*pDMA6_CONFIG = (FLOW_ARRAY | NDSIZE_5 | WDSIZE_8 | DMAEN);
*pDMA5_CONFIG = 0x0;
*pDMA5_PERIPHERAL_MAP = 0x5000;
*pDMA5_CURR_DESC_PTR = (void *)&(spi_se->MISO_regs_addr);
*pDMA5_CONFIG = (FLOW_ARRAY | NDSIZE_5 | WNR | DI_EN | WDSIZE_8 | DMAEN );
ssync();
*pSPORT1_TCR1 |= TSPEN;
*pSPORT1_RCR1 |= RSPEN;
ssync();
// #if (!defined(asynchronous_SPORT))
while(*pSPORT1_RCR1 & RSPEN);
// #endif
}
return;
}
void SendSingleCommand(u8 addr)
{
static u8 phaser_reg_addr;
sm_sport_desc_t *spi_wren;
if(!(*pSPORT1_RCR1 & RSPEN)) {
phaser_reg_addr = addr;
// update descriptors
spi_wren = &spi_wren_desc;
spi_wren->MOSI_regs_addr.START_ADDR_L = ((u32)&phaser_reg_addr & 0xFFFF);
spi_wren->MOSI_regs_addr.START_ADDR_H = (((u32)&phaser_reg_addr >> 16) & 0xFFFF);
// now DMA
*pDMA6_CONFIG = 0x0;
*pDMA6_PERIPHERAL_MAP = 0x6000;
*pDMA6_CURR_DESC_PTR = (void *)&(spi_wren->MOSI_regs_addr);
*pDMA6_CONFIG = (FLOW_ARRAY | NDSIZE_5 | WDSIZE_8 | DMAEN);
*pDMA5_CONFIG = 0x0;
*pDMA5_PERIPHERAL_MAP = 0x5000;
*pDMA5_CURR_DESC_PTR = (void *)&(spi_wren->MISO_regs_addr);
*pDMA5_CONFIG = (FLOW_ARRAY | NDSIZE_5 | WNR | WDSIZE_8 | DMAEN | DI_EN);
ssync();
*pSPORT1_TCR1 |= TSPEN;
*pSPORT1_RCR1 |= RSPEN;
ssync();
// #if (!defined(asynchronous_SPORT))
while(*pSPORT1_RCR1 & RSPEN);
// #endif
}
return;
}
//--------------------------------------------------------------------------//
// Function: sm_spi_read_8bits
//
// Parameters: u8 addr :
// u8 *data :
// int len :
//
// Return: int
//
// Description: sm_spi_read
//--------------------------------------------------------------------------//
int sm_spi_read_8bits(u8 addr, u8 *data, u32 len)
{
static u8 phaser_reg_addr;
sm_sport_desc_t *read_8bits;
u8 ret = 1;
if(!(*pSPORT1_RCR1 & RSPEN))
{
phaser_reg_addr = addr;
// update descriptors
read_8bits = &sm_sport_read_8bits_desc;
read_8bits->MOSI_regs_addr.START_ADDR_L = ((u32)&phaser_reg_addr & 0xFFFF);
read_8bits->MOSI_regs_addr.START_ADDR_H = (((u32)&phaser_reg_addr >> 16) & 0xFFFF);
read_8bits->MOSI_regs_value.X_CNT = len;
read_8bits->MISO_regs_value.START_ADDR_L = ((u32)data & 0xFFFF);
read_8bits->MISO_regs_value.START_ADDR_H = (((u32)data >> 16) & 0xFFFF);
read_8bits->MISO_regs_value.X_CNT = len;
// now DMA
*pDMA6_CONFIG = 0x0;
*pDMA6_PERIPHERAL_MAP = 0x6000;
*pDMA6_CURR_DESC_PTR = (void *)&(read_8bits->MOSI_regs_addr);
*pDMA6_CONFIG = (FLOW_ARRAY | NDSIZE_5 | WDSIZE_8 | DMAEN);
*pDMA5_CONFIG = 0x0;
*pDMA5_PERIPHERAL_MAP = 0x5000;
*pDMA5_CURR_DESC_PTR = (void *)&(read_8bits->MISO_regs_addr);
*pDMA5_CONFIG = (FLOW_ARRAY | NDSIZE_5 | WDSIZE_8 | DMAEN);
ssync();
*pSPORT1_TCR1 |= TSPEN;
*pSPORT1_RCR1 |= RSPEN;
ssync();
//#if (!defined(asynchronous_SPORT))
while(*pSPORT1_RCR1 & RSPEN);
//#endif
ret = 0;
}
return ret;
}
//--------------------------------------------------------------------------//
// Function: sm_spi_write_8bits
//
// Parameters: u8 addr :
// u8 *data :
// int len :
//
// Return: int
//
// Description: sm_spi_write
//--------------------------------------------------------------------------//
//void sm_spi_read_multiple_8bits(u8 opcode, u8 *addr, u8 *datain, u32 len)
void sm_spi_write_8bits(u8 opcode, u8 *addr, u8 *dataout, u32 len, u32 modify)
{
static u8 phaser_opcode;
sm_sport_desc_t *write_8bits;
if (!(*pSPORT1_RCR1 & RSPEN))
{
phaser_opcode = opcode;
// update descriptors
write_8bits = &sm_sport_write_8bits_desc;
write_8bits->MOSI_regs_addr.START_ADDR_L = ((u32)&phaser_opcode & 0xFFFF); // MOSI - register addr phase
write_8bits->MOSI_regs_addr.START_ADDR_H = (((u32)&phaser_opcode >> 16) & 0xFFFF);
write_8bits->MOSI_regs_value.START_ADDR_L = ((u32)addr & 0xFFFF); // MOSI - register addr phase
write_8bits->MOSI_regs_value.START_ADDR_H = (((u32)addr >> 16) & 0xFFFF);
write_8bits->MOSI_regs_value2.START_ADDR_L = ((u32)dataout & 0xFFFF); // MOSI - register addr phase
write_8bits->MOSI_regs_value2.START_ADDR_H = (((u32)dataout >> 16) & 0xFFFF);
write_8bits->MOSI_regs_value2.X_CNT = len;
write_8bits->MOSI_regs_value2.X_MOD = modify;
write_8bits->MISO_regs_value.X_CNT = len;
// now DMA
*pDMA6_CONFIG = 0x0;
*pDMA6_PERIPHERAL_MAP = 0x6000;
*pDMA6_CURR_DESC_PTR = (void *)&(write_8bits->MOSI_regs_addr);
*pDMA6_CONFIG = (FLOW_ARRAY | NDSIZE_5 | WDSIZE_8 | DMAEN);
*pDMA5_CONFIG = 0x0;
*pDMA5_PERIPHERAL_MAP = 0x5000;
*pDMA5_CURR_DESC_PTR = (void *)&(write_8bits->MISO_regs_addr);
*pDMA5_CONFIG = FLOW_ARRAY | NDSIZE_5 | DI_EN | WNR | WDSIZE_8 | DMAEN;
ssync();
*pSPORT1_TCR1 |= TSPEN;
*pSPORT1_RCR1 |= RSPEN;
ssync();
//#if (!defined(asynchronous_SPORT))
while(*pSPORT1_RCR1 & RSPEN);
//#endif
}
return;
}
void sm_spi_read_multiple_8bits(u8 opcode, u8 *addr, u8 *datain, u32 len)
{
static u8 phaser_opcode;
sm_sport_desc_t *read_multiple_8bits;
if (!(*pSPORT1_RCR1 & RSPEN))
{
phaser_opcode = opcode;
// update descriptors
read_multiple_8bits = &sm_sport_read_multiple_8bits_desc;
// 'MOSI' desc - register addr phase - START_ADDR modified in sm_sport_read_multiple_8bits desc
read_multiple_8bits->MOSI_regs_addr.START_ADDR_L = ((u32)(&(phaser_opcode)) & 0xFFFF);
read_multiple_8bits->MOSI_regs_addr.START_ADDR_H = (((u32)(&(phaser_opcode)) >> 16) & 0xFFFF);
// 'MOSI desc - register value phase - START_ADDR modified in sm_sport_read_multiple_8bits desc
read_multiple_8bits->MOSI_regs_value.START_ADDR_L = ((u32)(addr) & 0xFFFF);
read_multiple_8bits->MOSI_regs_value.START_ADDR_H = (((u32)(addr) >> 16) & 0xFFFF);
// 'MOSI desc - register value phase - X_COUNT modified in sm_sport_read_multiple_8bits desc
// 'MISO' desc - register value phase - START_ADDR and X_COUNT modified in sm_sport_read_multiple_8bits desc
#ifdef ATMEL_DATAFLASH //4 dummy reads are required
read_multiple_8bits->MOSI_regs_value2.X_CNT = len+4;
read_multiple_8bits->MISO_regs_addr.X_CNT = 8;
else
read_multiple_8bits->MOSI_regs_value2.X_CNT = len;
#endif
read_multiple_8bits->MISO_regs_value.START_ADDR_L = ((u32)(datain) & 0xFFFF);
read_multiple_8bits->MISO_regs_value.START_ADDR_H = (((u32)(datain) >> 16) & 0xFFFF);
read_multiple_8bits->MISO_regs_value.X_CNT = len;
// now DMA
*pDMA6_CONFIG = 0x0;
*pDMA6_PERIPHERAL_MAP = 0x6000;
*pDMA6_CURR_DESC_PTR = (void *)&(read_multiple_8bits->MOSI_regs_addr);
*pDMA6_CONFIG = (FLOW_ARRAY | NDSIZE_5 | WDSIZE_8 | DMAEN);
*pDMA5_CONFIG = 0x0;
*pDMA5_PERIPHERAL_MAP = 0x5000;
*pDMA5_CURR_DESC_PTR = (void *)&(read_multiple_8bits->MISO_regs_addr);
*pDMA5_CONFIG = FLOW_ARRAY | NDSIZE_5 | WNR | WDSIZE_8 | DMAEN;
ssync();
*pSPORT1_TCR1 |= TSPEN;
*pSPORT1_RCR1 |= RSPEN;
ssync();
//#if (!defined(asynchronous_SPORT))
while(*pSPORT1_RCR1 & RSPEN);
//#endif
}
return;
}
//--------------------------------------------------------------------------//
// Function: SPORT1_ISR //
// //
// //
// Parameters: None //
// //
// Return: None //
// //
// Description: SPORT1_ISR //
//--------------------------------------------------------------------------//
EX_INTERRUPT_HANDLER(SPORT1_ISR)
{
if (*pDMA5_IRQ_STATUS & DMA_DONE)
*pDMA5_IRQ_STATUS |= DMA_DONE; // Signal that interrupt has been serviced
if (*pDMA6_IRQ_STATUS & DMA_DONE)
*pDMA6_IRQ_STATUS |= DMA_DONE; // Signal that interrupt has been serviced
*pSPORT1_TCR1 &= ~(TSPEN);
*pSPORT1_RCR1 &= ~(RSPEN);
ssync();
}/* End of SPORT1_ISR */
//--------------------------------------------------------------------------//
// Function: SYS_ERR_ISR //
// //
// //
// Parameters: None //
// //
// Return: None //
// //
// Description: Generic SYS_ERR ISR //
//--------------------------------------------------------------------------//
EX_INTERRUPT_HANDLER(SYS_ERR_ISR)
{
if (*pSPORT1_STAT & (TUVF|TOVF))
*pSPORT1_STAT |= (TUVF|TOVF); // clear SPORT0 Errors
if (*pDMA5_IRQ_STATUS & DMA_ERR)
*pDMA5_IRQ_STATUS |= DMA_ERR; // SPORT - Signal that interrupt has been serviced
if (*pDMA6_IRQ_STATUS & DMA_ERR)
*pDMA6_IRQ_STATUS |= DMA_ERR; // SPORT - Signal that interrupt has been serviced
ssync();
while(1);
//while(1); // wait here
}/* End of SYS_ERR_ISR */
//--------------------------------------------------------------------------//
// Function: HW_ERR_ISR //
// //
// //
// Parameters: None //
// //
// Return: None //
// //
// Description: Generic HW_ERR ISR //
//--------------------------------------------------------------------------//
EX_INTERRUPT_HANDLER(HW_ERR_ISR)
{
while(1); // wait here
}/* End of HW_ERR_ISR */
//--------------------------------------------------------------------------//
// Function: EXCEP_ISR //
// //
// //
// Parameters: None //
// //
// Return: None //
// //
// Description: Generic EXCEPTION ISR //
//--------------------------------------------------------------------------//
EX_INTERRUPT_HANDLER(EXCEP_ISR)
{
while(1); // wait here
}/* End of EXCEP_ISR */
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