main.c

是bf533使用SPORT模拟SPI通信的实例

			// Based on the address where to start programming this sector must be erased before. 
			// The function GET_SECTNUM will return the sector number where the start address points to.
			// The sector number will than be taken to run the EraseBlock function.
			case GET_SECTNUM:

				AFP_Error = GetSectorNumber( AFP_Offset, &AFP_Sector );
			break;
			
			// no command or unknown command do nothing
			case NO_COMMAND:
				default:
				// set our error
				AFP_Error = UNKNOWN_COMMAND;
				break;
		}

		// clear the command
		AFP_Command = NO_COMMAND;
	}

// free the buffer if we were able to allocate one
	if ( AFP_Buffer )
		free( AFP_Buffer );
	// all done
	return 0;
}

//--------------------------------------------------------------------------//
// Function:	Init_SPORT													//
//																			//
// Parameters:	None														//
//																			//
// Return:		None														//
//																			//
// Description:	This function sets up the SPORT								//
//--------------------------------------------------------------------------//
void Init_SPORT(void)
{
    *pSIC_IMASK = 	  SIC_MASK(SPORT1_TX_PID) 			// SPORT1_TX
					| SIC_MASK(SPORT1_RX_PID)			// SPORT1_RX
#if 0
					| SIC_MASK(SPORT1_ERR) 				// SPORT1 Errors
#endif
					| SIC_MASK(DMA_ERR);				// DMA error

	register_handler_ex (ik_exception, EXCEP_ISR, EX_INT_ENABLE);		// assign ISR to system exception
	register_handler_ex (ik_hardware_err, HW_ERR_ISR, EX_INT_ENABLE);	// assign ISR to HW_ERR
	register_handler_ex (ik_ivg7, SYS_ERR_ISR, EX_INT_ENABLE);			// assign ISR to System Error interrupt
	register_handler_ex (ik_ivg9, SPORT1_ISR, EX_INT_ENABLE);			// assign ISR to SPORT0_TX DMA interrupt

	*pPORTG_FER 		= (0x3F)<<10;
	*pPORT_MUX 			= PGTE | PGRE;
	
	*pSPORT1_TCLKDIV	= 0;							// SPORT CLK = SCLK/2 (45MHz)
	*pSPORT1_TFSDIV		= 0x7;							// SPORT TFS every 8 SPORT CLK cycles 
	*pSPORT1_TCR2		= SLEN(0x7);					// TX word length 8 bit
	*pSPORT1_TCR1		= TCKFE | LATFS	| LTFS | TFSR | ITFS | ITCLK;  

	*pSPORT1_RCLKDIV	= 0;							// SPORT CLK = SCLK/2 (45MHz)
	*pSPORT1_RFSDIV		= 0x7;							// SPORT RFS every 8 SPORT CLK cycles 
	*pSPORT1_RCR2		= SLEN(0x7);					// RX word length 8 bit
	*pSPORT1_RCR1		= RCKFE | LARFS	| LRFS | RFSR;
}


//--------------------------------------------------------------------------//
// Function:	Init_Descriptors											//
//																			//
// Parameters:	None														//
//																			//
// Return:		None														//
//																			//
// Description:	This function initializes the descriptor structures			//
//--------------------------------------------------------------------------//
void Init_Descriptors(void)
{
    sm_sport_desc_t *spi_wren, *spi_se, *read_8bits, *write_8bits, *read_multiple_8bits;
    
    //SendSingleCommand(u8 addr)
    spi_wren = &spi_wren_desc;
    // 'MOSI' desc - register addr phase - START_ADDR modified in SendSingleCommand(u8 addr)
    spi_wren->MOSI_regs_addr.CONFIG				= (FLOW_STOP | NDSIZE_0 | WDSIZE_8 | DMAEN);
	spi_wren->MOSI_regs_addr.X_CNT				= 1;
	spi_wren->MOSI_regs_addr.X_MOD				= 0;
	
	// 'MISO' desc - register addr phase - no modifications required
	spi_wren->MISO_regs_addr.START_ADDR_L		= ((u32)(&(spi_wren->dummy_read))  & 0xFFFF);
	spi_wren->MISO_regs_addr.START_ADDR_H		= (((u32)(&(spi_wren->dummy_read)) >> 16) & 0xFFFF);
	spi_wren->MISO_regs_addr.CONFIG				= (FLOW_STOP | NDSIZE_0 | WNR | WDSIZE_8 | DMAEN | DI_EN);
	spi_wren->MISO_regs_addr.X_CNT				= 1;
	spi_wren->MISO_regs_addr.X_MOD				= 0;			
	
	//SectorErase(u8 opcode, u8* addr)
	spi_se = &spi_se_desc;
	// 'MOSI' desc - register addr phase - START_ADDR modified in SectorErase
	spi_se->MOSI_regs_addr.CONFIG			= (FLOW_ARRAY | NDSIZE_5 | WDSIZE_8| DMAEN);
	spi_se->MOSI_regs_addr.X_CNT			= 1;
	spi_se->MOSI_regs_addr.X_MOD			= 0;
	// 'MOSI desc - register value phase - START_ADDR modified in SectorErase
	spi_se->MOSI_regs_value.CONFIG		    = (FLOW_STOP | NDSIZE_0 | WDSIZE_8| DMAEN);
	spi_se->MOSI_regs_value.X_CNT			= 3;
	spi_se->MOSI_regs_value.X_MOD			= 1;
	// 'MISO' desc - register addr phase - no modifications required
	spi_se->MISO_regs_addr.START_ADDR_L		= ((u32)(&(spi_se->dummy_read))  & 0xFFFF);
	spi_se->MISO_regs_addr.START_ADDR_H		= (((u32)(&(spi_se->dummy_read)) >> 16) & 0xFFFF);
	spi_se->MISO_regs_addr.CONFIG			= (FLOW_STOP | NDSIZE_0 | DI_EN | WNR | WDSIZE_8 | DMAEN);
	spi_se->MISO_regs_addr.X_CNT			= 4;
	spi_se->MISO_regs_addr.X_MOD			= 0;			
	
    //sm_spi_read_8bits(u8 addr, u8 *data, u32 len)
	read_8bits = &sm_sport_read_8bits_desc;
	// 'MOSI' desc - register addr phase - START_ADDR modified in sm_spi_read_8bits(u8 addr, u8 *data, u32 len)
	read_8bits->MOSI_regs_addr.CONFIG			= (FLOW_ARRAY | NDSIZE_5 | WDSIZE_8| DMAEN);
	read_8bits->MOSI_regs_addr.X_CNT			= 1;
	read_8bits->MOSI_regs_addr.X_MOD			= 1;
	
	// 'MOSI desc - register value phase - X_CNT modified in sm_spi_read_8bits
	read_8bits->MOSI_regs_value.START_ADDR_L	= ((u32)(&(read_8bits->dummy_write))  & 0xFFFF);
	read_8bits->MOSI_regs_value.START_ADDR_H	= (((u32)(&(read_8bits->dummy_write)) >> 16) & 0xFFFF);
	read_8bits->MOSI_regs_value.CONFIG		    = (FLOW_STOP | NDSIZE_0 | WDSIZE_8| DMAEN);
	read_8bits->MOSI_regs_value.X_MOD			= 0;
	
	// 'MISO' desc - register addr phase - no modifications required
	read_8bits->MISO_regs_addr.START_ADDR_L	    = ((u32)(&(read_8bits->dummy_read))  & 0xFFFF);
	read_8bits->MISO_regs_addr.START_ADDR_H	    = (((u32)(&(read_8bits->dummy_read)) >> 16) & 0xFFFF);
	read_8bits->MISO_regs_addr.CONFIG			= (FLOW_ARRAY | NDSIZE_5 | WNR | WDSIZE_8 | DMAEN);
	read_8bits->MISO_regs_addr.X_CNT			= 1;
	read_8bits->MISO_regs_addr.X_MOD			= 0;
	
	// 'MISO' desc - register value phase - START_ADDR and X_CNT modified in sm_spi_read_8bits
	read_8bits->MISO_regs_value.CONFIG		    = (FLOW_STOP | NDSIZE_0 | DI_EN | WNR | WDSIZE_8 | DMAEN);
	read_8bits->MISO_regs_value.X_MOD			= 1;		
	
	//sm_spi_write_8bits(u8 opcode, u8 *addr, u8 *dataout u32 len, u32 modify)
	write_8bits = &sm_sport_write_8bits_desc;
	
	// 'MOSI' desc - register addr phase - START_ADDR modified in sm_spi_write_8bits
	write_8bits->MOSI_regs_addr.CONFIG			= (FLOW_ARRAY | NDSIZE_5 | WDSIZE_8| DMAEN);
	write_8bits->MOSI_regs_addr.X_CNT			= 1;
	write_8bits->MOSI_regs_addr.X_MOD			= 0;
	
	// 'MOSI desc - register value phase - START_ADDR modified in sm_spi_write_8bits
	write_8bits->MOSI_regs_value.CONFIG		    = (FLOW_ARRAY | NDSIZE_5 | WDSIZE_8| DMAEN);
	write_8bits->MOSI_regs_value.X_CNT			= 3;
	write_8bits->MOSI_regs_value.X_MOD			= 1;
	
	// 'MOSI desc - register value phase - START_ADDR, X_COUNT, X_MOD modified in sm_spi_write_8bits
	write_8bits->MOSI_regs_value2.CONFIG		= (FLOW_STOP | NDSIZE_0 | WDSIZE_8| DMAEN);	
			
	// 'MISO' desc - register addr phase - no modifications required
	write_8bits->MISO_regs_addr.START_ADDR_L	= ((u32)(&(write_8bits->dummy_read))  & 0xFFFF);
	write_8bits->MISO_regs_addr.START_ADDR_H	= (((u32)(&(write_8bits->dummy_read)) >> 16) & 0xFFFF);
	write_8bits->MISO_regs_addr.CONFIG			= (FLOW_ARRAY | NDSIZE_5 | WNR | WDSIZE_8 | DMAEN);
	write_8bits->MISO_regs_addr.X_CNT			= 4;
	write_8bits->MISO_regs_addr.X_MOD			= 0;
	
	// 'MISO' desc - register value phase - X_CNT modified in sm_spi_write_8bits
	write_8bits->MISO_regs_value.START_ADDR_L	= ((u32)(&(write_8bits->dummy_read))  & 0xFFFF);
	write_8bits->MISO_regs_value.START_ADDR_H	= (((u32)(&(write_8bits->dummy_read)) >> 16) & 0xFFFF);
	write_8bits->MISO_regs_value.CONFIG			= (FLOW_STOP | NDSIZE_0 | DI_EN | WNR | WDSIZE_8 | DMAEN);
	write_8bits->MISO_regs_value.X_MOD			= 0;
			
	//sm_spi_read_multiple_8bits(u8 opcode, u8 *addr, u8 *datain, u32 len)
	read_multiple_8bits = &sm_sport_read_multiple_8bits_desc;
	
	// 'MOSI' desc - register addr phase - START_ADDR modified in sm_sport_read_multiple_8bits desc
	read_multiple_8bits->MOSI_regs_addr.CONFIG			= (FLOW_ARRAY | NDSIZE_5 | WDSIZE_8| DMAEN);
	read_multiple_8bits->MOSI_regs_addr.X_CNT			= 1;
	read_multiple_8bits->MOSI_regs_addr.X_MOD			= 0;
	
	// 'MOSI desc - register value phase - START_ADDR modified in sm_sport_read_multiple_8bits desc
	read_multiple_8bits->MOSI_regs_value.CONFIG		    = (FLOW_ARRAY | NDSIZE_5 | WDSIZE_8| DMAEN);
	read_multiple_8bits->MOSI_regs_value.X_CNT			= 3;
	read_multiple_8bits->MOSI_regs_value.X_MOD			= 1;
	
	// 'MOSI desc - register value phase - X_COUNT modified in sm_sport_read_multiple_8bits desc
	read_multiple_8bits->MOSI_regs_value2.START_ADDR_L	= ((u32)(&(read_multiple_8bits->dummy_write))  & 0xFFFF);
	read_multiple_8bits->MOSI_regs_value2.START_ADDR_H	= (((u32)(&(read_multiple_8bits->dummy_write)) >> 16) & 0xFFFF);
	read_multiple_8bits->MOSI_regs_value2.CONFIG		= (FLOW_STOP | NDSIZE_0 | WDSIZE_8| DMAEN);	
	read_multiple_8bits->MOSI_regs_value2.X_MOD			= 0;		
		
	// 'MISO' desc - register addr phase - no modifications required
	read_multiple_8bits->MISO_regs_addr.START_ADDR_L	= ((u32)(&(read_multiple_8bits->dummy_read))  & 0xFFFF);
	read_multiple_8bits->MISO_regs_addr.START_ADDR_H	= (((u32)(&(read_multiple_8bits->dummy_read)) >> 16) & 0xFFFF);
	read_multiple_8bits->MISO_regs_addr.CONFIG			= (FLOW_ARRAY | NDSIZE_5 | WNR | WDSIZE_8 | DMAEN);
	read_multiple_8bits->MISO_regs_addr.X_CNT			= 4;
	read_multiple_8bits->MISO_regs_addr.X_MOD			= 0;
	// 'MISO' desc - register value phase - START_ADDR and X_COUNT modified in sm_sport_read_multiple_8bits desc 
	read_multiple_8bits->MISO_regs_value.CONFIG			= (FLOW_STOP | NDSIZE_0 | DI_EN | WNR | WDSIZE_8 | DMAEN);
	read_multiple_8bits->MISO_regs_value.X_MOD			= 1;	

}// end of Init_Descriptors

//////////////////////////////////////////////////////////////
// ERROR_CODE GetCodes()
//
// Sector Table Setup for a certain device
//
//////////////////////////////////////////////////////////////

ERROR_CODE GetCodes()
{
	// This function makes use of the settings in the file "SPI_Device_Settings.h".
	
	// In regards to the device chosen the sectors will be organized.
	AFP_NumSectors = SPI_SECTORS;
	AFP_SectorSize = SPI_SECTOR_SIZE;

	SectorInfo[0].lStartOff = SECTORBASE;
	SectorInfo[0].lEndOff =   SECTORBASE + SPI_SECTOR_SIZE - 1;
	SectorInfo[1].lStartOff = SECTORBASE + SPI_SECTOR_SIZE;
	SectorInfo[1].lEndOff =   SECTORBASE + 2 * SPI_SECTOR_SIZE - 1;
	SectorInfo[2].lStartOff = SECTORBASE + 2 * SPI_SECTOR_SIZE;
	SectorInfo[2].lEndOff =   SECTORBASE + 3 * SPI_SECTOR_SIZE - 1;
	SectorInfo[3].lStartOff = SECTORBASE + 3 * SPI_SECTOR_SIZE;
	SectorInfo[3].lEndOff =   SECTORBASE + 4 * SPI_SECTOR_SIZE - 1;


	return NO_ERR;
	
}


//////////////////////////////////////////////////////////////
// ERROR_CODE EraseFlash()
//
// Sends an "erase all" command to the flash.
//
//////////////////////////////////////////////////////////////

ERROR_CODE EraseFlash()
{
	
	ERROR_CODE ErrorCode = NO_ERR;
	
	//A write enable instruction must previously have been executed
	SendSingleCommand(SPI_WREN);
 	
	//The status register will be polled to check the write enable latch "WREN"
	ErrorCode = Wait_For_nStatus();

	if( POLL_TIMEOUT == ErrorCode )
	{
		return ErrorCode;
	}
	else

	SendSingleCommand(SPI_BE);
 		
	// Erasing the whole flash will take time, so the following bit must be polled.
	//The status register will be polled to check the write in progress bit "WIP"
	ErrorCode = Wait_For_Status(WIP);
	
	return ErrorCode;
}

//////////////////////////////////////////////////////////////
// ERROR_CODE ResetFlash()
//
// This function sends a Write Disable Command to the SPI device
// After that it checks the Write Enable Latch.
//
//////////////////////////////////////////////////////////////

ERROR_CODE ResetFlash()
{
	char status_register = 0;
	ERROR_CODE ErrorCode = NO_ERR;	
	
	SendSingleCommand(SPI_WRDI);
	ErrorCode = Wait_For_Status(WEL);
	
	// reset should be complete
	return ErrorCode;
}


//////////////////////////////////////////////////////////////
// ERROR_CODE EraseBlock()
//
// Sends an "erase block" command to the flash.
//
//////////////////////////////////////////////////////////////

ERROR_CODE EraseBlock( int nBlock )
{
	unsigned long ulSectorOff = 0x0;
	unsigned char ShiftValue[3];
	ERROR_CODE ErrorCode = NO_ERR;	


	// if the block is invalid "out of possible rangs" just return with an error.
	if ( (nBlock < 0) || (nBlock > AFP_NumSectors) )
	{
		ErrorCode = INVALID_BLOCK;	// tells us if there was an error erasing flash
		return ErrorCode;
	}
	
	// figure out the offset of the block in flash
	if ( (nBlock >= 0) && (nBlock < AFP_NumSectors) )
	{
		ulSectorOff = (nBlock * AFP_SectorSize);
		
	}
	else
	{
		ErrorCode = INVALID_BLOCK;	// tells us if there was an error erasing flash
		return ErrorCode;
	}

	// A write enable instruction must previously have been executed
	SendSingleCommand(SPI_WREN);
	
	//The status register will be polled to check the write enable latch "WREN"
	ErrorCode = Wait_For_nStatus();
	
	if( POLL_TIMEOUT == ErrorCode )
	{
		return ErrorCode;
	}
	else

	// Send the erase block command to the flash followed by the address 
	// to point to the start of a sector.
	ShiftValue[0] = ulSectorOff >> 16;
	ShiftValue[1] = ulSectorOff >> 8;
	ShiftValue[2] = ulSectorOff;	
	SectorErase(SPI_SE,(u8*) &ShiftValue[0]);