📄 s2410.h
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#define BIT_DMA2 (0x1<<19)
#define BIT_DMA3 (0x1<<20)
#define BIT_MMC (0x1<<21)
#define BIT_SPI0 (0x1<<22)
#define BIT_UART1 (0x1<<23)
#define BIT_RSV2 (0x1<<24)
#define BIT_USBD (0x1<<25)
#define BIT_USBH (0x1<<26)
#define BIT_IIC (0x1<<27)
#define BIT_UART0 (0x1<<28)
#define BIT_SPI1 (0x1<<29)
#define BIT_RTC (0x1<<30)
#define BIT_ADC (0x1<<31)
#define BIT_ALLMSK (0xffffffff)
#define BIT_SUB_ADC (0x1<<10)
#define BIT_SUB_TC (0x1<<9)
#define BIT_SUB_ERR2 (0x1<<8)
#define BIT_SUB_TXD2 (0x1<<7)
#define BIT_SUB_RXD2 (0x1<<6)
#define BIT_SUB_ERR1 (0x1<<5)
#define BIT_SUB_TXD1 (0x1<<4)
#define BIT_SUB_RXD1 (0x1<<3)
#define BIT_SUB_ERR0 (0x1<<2)
#define BIT_SUB_TXD0 (0x1<<1)
#define BIT_SUB_RXD0 (0x1<<0)
#define BIT_SUB_ALLMSK (0x7ff)
// S3C2410X01 Interrupt controller source number
#define INTSRC_EINT0 0
#define INTSRC_EINT1 1
#define INTSRC_EINT2 2
#define INTSRC_EINT3 3
#define INTSRC_EINT4_7 4
#define INTSRC_EINT8_23 5
#define INTSRC_RSV1 6
#define INTSRC_BAT_FLT 7
#define INTSRC_TICK 8
#define INTSRC_WDT 9
#define INTSRC_TIMER0 10
#define INTSRC_TIMER1 11
#define INTSRC_TIMER2 12
#define INTSRC_TIMER3 13
#define INTSRC_TIMER4 14
#define INTSRC_UART2 15
#define INTSRC_LCD 16
#define INTSRC_DMA0 17
#define INTSRC_DMA1 18
#define INTSRC_DMA2 19
#define INTSRC_DMA3 20
#define INTSRC_MMC 21
#define INTSRC_SPI0 22
#define INTSRC_UART1 23
#define INTSRC_RSV2 24
#define INTSRC_USBD 25
#define INTSRC_USBH 26
#define INTSRC_IIC 27
#define INTSRC_UART0 28
#define INTSRC_SPI1 29
#define INTSRC_RTC 30
#define INTSRC_ADC 31
#define INTSRC_ALLMSK (0xffffffff)
// S3C2410X01 Interrupt controller bit positions
// For SUB source pending bit.
#define INTSUB_RXD0 (0x1 << 0)
#define INTSUB_TXD0 (0x1 << 1)
#define INTSUB_ERR0 (0x1 << 2)
#define INTSUB_RXD1 (0x1 << 3)
#define INTSUB_TXD1 (0x1 << 4)
#define INTSUB_ERR1 (0x1 << 5)
#define INTSUB_RXD2 (0x1 << 6)
#define INTSUB_TXD2 (0x1 << 7)
#define INTSUB_ERR2 (0x1 << 8)
#define INTSUB_TC (0x1 << 9)
#define INTSUB_ADC (0x1 << 10)
#define INTSUB_SLLMSK (0xFFFFFFFF)
#define INTSUB_BASE 0xB0A00018 // 0x4A000018 // serial
#define INTSUB_MSK 0xB0A0001C // 0x4A00001C // serial
#define BIT_SUB_ALLMSK (0x7ff)
//
// Registers : LCD Controller
//
#define LCD_BASE 0xB0D00000 // 0x4D000000
typedef struct {
unsigned int rLCDCON1; // 00
unsigned int rLCDCON2; // 04
unsigned int rLCDCON3; // 08
unsigned int rLCDCON4; // 0C
unsigned int rLCDCON5; // 10
unsigned int rLCDSADDR1; // 14
unsigned int rLCDSADDR2; // 18
unsigned int rLCDSADDR3; // 1C
unsigned int rREDLUT; // 20
unsigned int rGREENLUT; // 24
unsigned int rBLUELUT; // 28
unsigned int rPAD[8]; // 2C - 48
unsigned int rDITHMODE; // 4C
unsigned int rTPAL; // 50
unsigned int rLCDINTPND; // 54
unsigned int rLCDSRCPND; // 58
unsigned int rLCDINTMSK; // 5C
unsigned int rLPCSEL; // 60
}LCDreg ;
// LCD register value...
#define MODE_STN_1BIT (1)
#define MODE_STN_2BIT (2)
#define MODE_STN_4BIT (4)
#define MODE_CSTN_8BIT (108)
#define MODE_CSTN_12BIT (112)
#define MODE_TFT_1BIT (201)
//#define MODE_TFT_2BIT (202)
//#define MODE_TFT_4BIT (204)
#define MODE_TFT_8BIT (208)
#define MODE_TFT_16BIT (216)
/*
=1/((C3+D3+E3+F3+4)*(G3+H3+I3+J3+4)*(2*(K3+1)/L3))
=1/((C4+D4+E4+F4+4)*(G4+H4+I4+J4+4)*(2*(K4+1)/L4))
=1/((C5+D5+E5+F5+4)*(G5+H5+I5+J5+4)*(2*(K5+1)/L5))
=1/((C6+D6+E6+F6+4)*(G6+H6+I6+J6+4)*(2*(K6+1)/L6))
=1/((C7+D7+E7+F7+4)*(G7+H7+I7+J7+4)*(2*(K7+1)/L7))
=1/((C8+D8+E8+F8+4)*(G8+H8+I8+J8+4)*(2*(K8+1)/L8))
=1/((C9+D9+E9+F9+4)*(G9+H9+I9+J9+4)*(2*(K9+1)/L9))
=1/((C10+D10+E10+F10+4)*(G10+H10+I10+J10+4)*(2*(K10+1)/L10))
=1/((C11+D11+E11+F11+4)*(G11+H11+I11+J11+4)*(2*(K11+1)/L11))
*/
#if ( LCD_SCREEN_SIZE == 3 )
#define LCD_XSIZE_TFT (320)
#define LCD_YSIZE_TFT (240)
#define LCD_FRAMEBUFFER_SIZE (0x28000)//28000
#define VSPW ((2-1)&0x3f)
#define VBPD ((2-1)&0xff)
#define VFPD ((3-1)&0xff)
#define HSPW ((4-1)&0xff) //yf=4 linux=5
#define HBPD ((7-1)&0x7f)
#define HFPD ((3-1)&0xff)
#define CLKVAL_TFT (6) //yf=6 linux=1
#endif
#if ( LCD_SCREEN_SIZE == 4 )
#define LCD_XSIZE_TFT (240)
#define LCD_YSIZE_TFT (320)
#define LCD_FRAMEBUFFER_SIZE (0x28000)//28000
#if 1 //yh
#define HSPW ((15-1)&0xff) //yf=4 linux=5
#define HBPD ((49-1)&0x7f)
#define HFPD ((2-1)&0xff)
#define VSPW ((3-1) &0x3f)
#define VBPD ((8-1)&0xff)
#define VFPD ((4-1)&0xff)
#define CLKVAL_TFT (5) //yf=6 linux=1
#else //jizhida
#define HSPW ((15-1)&0xff) //yf=4 linux=5
#define HBPD ((49-1)&0x7f)
#define HFPD ((2-1)&0xff)
#define VSPW ((3-1) &0x3f)
#define VBPD ((5-1)&0xff)
#define VFPD ((4-1)&0xff)
#define CLKVAL_TFT (5) //yf=6 linux=1
#define VSPW ((2-1) &0x3f)
#define VBPD ((2-1)&0xff)
#define VFPD ((3-1)&0xff)
#define HSPW ((4-1)&0xff) //yf=4 linux=5
#define HBPD ((7-1)&0x7f)
#define HFPD ((3-1)&0xff)
#define CLKVAL_TFT (5) //yf=6 linux=1
#endif
#endif
#if ( LCD_SCREEN_SIZE == 2 )
#define LCD_XSIZE_TFT (640)
#define LCD_YSIZE_TFT (480)
#define LCD_FRAMEBUFFER_SIZE (0xA0000)
#define VSPW ((2-1) &0x3f)
#define VBPD ((33-1)&0xff)
#define VFPD ((10-1)&0xff)
#define HSPW ((96-1)&0xff)
#define HBPD ((48-1)&0x7f)
#define HFPD ((16-1)&0xff)
#define CLKVAL_TFT (1)
/*
#define VSPW ((96-1) &0x3f) //夏普屏能点亮，但往下移1/3屏，颜色不正常？？？
#define VBPD ((48-1)&0xff)
#define VFPD ((16-1)&0xff)
#define HSPW ((2-1)&0xff)
#define HBPD ((33-1)&0x7f)
#define HFPD ((10-1)&0xff)
#define CLKVAL_TFT (1)
*/
#endif
#if ( LCD_SCREEN_SIZE == 1 )
#define LCD_XSIZE_TFT (800)
#define LCD_YSIZE_TFT (600)
#define LCD_FRAMEBUFFER_SIZE (0xF0000) //EA600
#define VSPW ((2-1) &0x3f)
#define VBPD ((33-1)&0xff)
#define VFPD ((10-1)&0xff)
#define HSPW ((96-1)&0xff)
#define HBPD ((48-1)&0x7f)
#define HFPD ((16-1)&0xff)
#ifdef LCD_IBM_800_600
#define VSPW ((3-1) &0x3f)
#define VBPD ((22-1)&0xff)
#define VFPD ((9-1)&0xff)
#define HSPW ((96-1)&0xff)
#define HBPD ((127-1)&0x7f)
#define HFPD ((16-1)&0xff)
#endif
#define CLKVAL_TFT (1)
#endif
#define SCR_XSIZE LCD_XSIZE_TFT //for virtual screen
#define SCR_YSIZE LCD_YSIZE_TFT
#define SCR_XSIZE_TFT (LCD_XSIZE_TFT*2) //for virtual screen
#define SCR_YSIZE_TFT (LCD_YSIZE_TFT*2)
#define LCD_XSIZE_STN (320)
#define LCD_YSIZE_STN (240)
#define LCD_XSIZE_CSTN (320)
#define LCD_YSIZE_CSTN (240)
//#define LCD_XSIZE_STN (240)
//#define LCD_YSIZE_STN (320)
//#define LCD_XSIZE_CSTN (240)
//#define LCD_YSIZE_CSTN (320)
#define ARRAY_SIZE_STN_1BIT (SCR_XSIZE/8*SCR_YSIZE)
#define ARRAY_SIZE_STN_2BIT (SCR_XSIZE/4*SCR_YSIZE)
#define ARRAY_SIZE_STN_4BIT (SCR_XSIZE/2*SCR_YSIZE)
#define ARRAY_SIZE_CSTN_8BIT (SCR_XSIZE/1*SCR_YSIZE)
#define ARRAY_SIZE_CSTN_12BIT (SCR_XSIZE*2*SCR_YSIZE)
#define ARRAY_SIZE_TFT_8BIT (SCR_XSIZE/1*SCR_YSIZE)
#define ARRAY_SIZE_TFT_16BIT (SCR_XSIZE*2*SCR_YSIZE)
#define HOZVAL_STN (LCD_XSIZE_STN/4-1)
#define LINEVAL_STN (LCD_YSIZE_STN-1)
#define HOZVAL_CSTN (LCD_XSIZE_CSTN*3/8-1)
#define LINEVAL_CSTN (LCD_YSIZE_CSTN-1)
#define HOZVAL_TFT (LCD_XSIZE_TFT-1)
#define LINEVAL_TFT (LCD_YSIZE_TFT-1)
//STN/CSTN timing parameter for LCBHBT161M(NANYA)
#define WLH (3)
#define WDLY (3)
#define LINEBLANK (1 &0xff)
//TFT timing parameter for V16C6448AB(PRIME VIEW)
#define MVAL (13)
#define MVAL_USED (0)
#define CLKVAL_STN_MONO (22)
//69.14hz @60Mhz,WLH=16clk,WDLY=16clk,LINEBLANK=1*8,VD=4
#define CLKVAL_STN_GRAY (12)
//124hz @60Mhz,WLH=16clk,WDLY=16clk,LINEBLANK=1*8,VD=4
#define CLKVAL_CSTN (8)
//135hz @60Mhz,WLH=16clk,WDLY=16clk,LINEBLANK=1*8,VD=8
//#define CLKVAL_TFT (7)
//NOTE: 1)SDRAM should have 32-bit bus width.
// 2)HBPD,HFPD,HSPW should be optimized.
//44.6hz @75Mhz
//VSYNC,HSYNC should be inverted
//HBPD=48VCLK,HFPD=16VCLK,HSPW=96VCLK
//VBPD=33HSYNC,VFPD=10HSYNC,VSPW=2HSYNC
#define M5D(n) ((n) & 0x1fffff)
//
// ADC
//
#define ADC_BASE 0xB1800000 // 0x58000000
typedef struct {
unsigned int rADCCON;
unsigned int rADCTSC;
unsigned int rADCDLY;
unsigned int rADCDAT0;
unsigned int rADCDAT1;
}ADCreg ;
//
// Registers : RTC
//
#define RTC_BASE 0xB1700000 // 0x57000000
typedef struct {
unsigned int rPAD1[16]; // 00 - 3C
unsigned int rRTCCON; // 40
unsigned int rTICINT;
unsigned int rPAD2[2];
unsigned int rRTCALM;
unsigned int rALMSEC;
unsigned int rALMMIN;
unsigned int rALMHOUR;
unsigned int rALMDAY;
unsigned int rALMMON;
unsigned int rALMYEAR;
unsigned int rRTCRST;
unsigned int rBCDSEC;
unsigned int rBCDMIN;
unsigned int rBCDHOUR;
unsigned int rBCDDAY;
unsigned int rBCDDATE;
unsigned int rBCDMON;
unsigned int rBCDYEAR;
} RTCreg;
#if 0 // _BIG_ENDIAN
#define rRTCCON (*(volatile unsigned char *)0xB1700043)
#define rRTCALM (*(volatile unsigned char *)0xB1700053)
#define rALMSEC (*(volatile unsigned char *)0xB1700057)
#define rALMMIN (*(volatile unsigned char *)0xB170005b)
#define rALMHOUR (*(volatile unsigned char *)0xB170005f)
#define rALMDAY (*(volatile unsigned char *)0xB1700063)
#define rALMMON (*(volatile unsigned char *)0xB1700067)
#define rALMYEAR (*(volatile unsigned char *)0xB170006b)
#define rRTCRST (*(volatile unsigned char *)0xB170006f)
#define rBCDSEC (*(volatile unsigned char *)0xB1700073)
#define rBCDMIN (*(volatile unsigned char *)0xB1700077)
#define rBCDHOUR (*(volatile unsigned char *)0xB170007b)
#define rBCDDAY (*(volatile unsigned char *)0xB170007f)
#define rBCDDATE (*(volatile unsigned char *)0xB1700083)
#define rBCDMON (*(volatile unsigned char *)0xB1700087)
#define rBCDYEAR (*(volatile unsigned char *)0xB170008b)
#define rTICINT (*(volatile unsigned char *)0xB1700047)
#endif
//
// Watch-Dog Timver
//
#define WATCH_BASE 0xB1300000 // 0x53000000
typedef struct {
unsigned long rWTCON;
unsigned long rWTDAT;
unsigned long rWTCNT;
} WATCHreg;
//
// SD / MMC
//
#define MMC_BACE 0xB1A00000 // 0x5A000000
typedef struct {
unsigned int rSDICON;
unsigned int rSDIPRE;
unsigned int rSDICMDARG;
unsigned int rSDICMDCON;
unsigned int rSDICMDSTA;
unsigned int rSDIRSP0;
unsigned int rSDIRSP1;
unsigned int rSDIRSP2;
unsigned int rSDIRSP3;
unsigned int rSDIDTIMER;
unsigned int rSDIBSIZE;
unsigned int rSDIDATCON;
unsigned int rSDIDATCNT;
unsigned int rSDIDATSTA;
unsigned int rSDIFSTA;
unsigned int rSDIDAT;
unsigned int rSDIINTMSK;
} MMCreg;
//
// IIC
//
#define IIC_BASE 0xB1400000 // 54000000
#define IICFIF_PHYS 0x54000000 // physical address of IIC
typedef struct {
unsigned int rIICCON;
unsigned int rIICSTAT;
unsigned int rIICADD;
unsigned int rIICDS;
}IICreg;
//
// IIS
//
#define IIS_BASE 0xB1500000
#define IISFIF_PHYS 0x55000010 // physical address of IISFIF for DMA
typedef struct {
unsigned int rIISCON;
unsigned int rIISMOD;
unsigned int rIISPSR;
unsigned int rIISFCON;
unsigned int rIISFIF;
}IISreg;
//
// SPI
//
#define SSP_BASE 0xB1900000 // 0x59000000
typedef struct {
unsigned int rSPCON0; // 00
unsigned int rSPSTA0;
unsigned int rSPPIN0;
unsigned int rSPPRE0;
unsigned int rSPTDAT0; // 10
unsigned int rSPRDAT0;
unsigned int rPAD[2];
unsigned int rSPCON1; // 20
unsigned int rSPSTA1;
unsigned int rSPPIN1;
unsigned int rSPPRE1;
unsigned int rSPTDAT1; // 30
unsigned int rSPRDAT1;
}SSPreg ;
#endif
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