cmd64x.c

ep9315平台下硬盘驱动的源码

/* $Id: cmd64x.c,v 1.21 2000/01/30 23:23:16
 *
 * linux/drivers/ide/pci/cmd64x.c		Version 1.30	Sept 10, 2002
 *
 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
 *           Note, this driver is not used at all on other systems because
 *           there the "BIOS" has done all of the following already.
 *           Due to massive hardware bugs, UltraDMA is only supported
 *           on the 646U2 and not on the 646U.
 *
 * Copyright (C) 1998		Eddie C. Dost  ([e-mail])
 * Copyright (C) 1998		David S. Miller ([e-mail])
 *
 * Copyright (C) 1999-2002	Andre Hedrick <[e-mail]>
 */

#include <linux/config.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/hdreg.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>

#include "ide_modes.h"
#include "cmd64x.h"

#if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS)
#include <linux/stat.h>
#include <linux/proc_fs.h>

static u8 cmd64x_proc = 0;

#define CMD_MAX_DEVS		5

static struct pci_dev *cmd_devs[CMD_MAX_DEVS];
static int n_cmd_devs;

#undef DEBUG_CMD_REGS

static char * print_cmd64x_get_info (char *buf, struct pci_dev *dev, int index)
{
	char *p = buf;

	u8 reg53 = 0, reg54 = 0, reg55 = 0, reg56 = 0;	/* primary */
	u8 reg57 = 0, reg58 = 0, reg5b;			/* secondary */
	u8 reg72 = 0, reg73 = 0;			/* primary */
	u8 reg7a = 0, reg7b = 0;			/* secondary */
	u8 reg50 = 0, reg71 = 0;			/* extra */
#ifdef DEBUG_CMD_REGS
	u8 hi_byte = 0, lo_byte = 0;
#endif /* DEBUG_CMD_REGS */

	p += sprintf(p, "\nController: %d\n", index);
	p += sprintf(p, "CMD%x Chipset.\n", dev->device);
	(void) pci_read_config_byte(dev, CFR,       &reg50);
	(void) pci_read_config_byte(dev, ARTTIM0,   &reg53);
	(void) pci_read_config_byte(dev, DRWTIM0,   &reg54);
	(void) pci_read_config_byte(dev, ARTTIM1,   &reg55);
	(void) pci_read_config_byte(dev, DRWTIM1,   &reg56);
	(void) pci_read_config_byte(dev, ARTTIM2,   &reg57);
	(void) pci_read_config_byte(dev, DRWTIM2,   &reg58);
	(void) pci_read_config_byte(dev, DRWTIM3,   &reg5b);
	(void) pci_read_config_byte(dev, MRDMODE,   &reg71);
	(void) pci_read_config_byte(dev, BMIDESR0,  &reg72);
	(void) pci_read_config_byte(dev, UDIDETCR0, &reg73);
	(void) pci_read_config_byte(dev, BMIDESR1,  &reg7a);
	(void) pci_read_config_byte(dev, UDIDETCR1, &reg7b);

	p += sprintf(p, "--------------- Primary Channel "
			"---------------- Secondary Channel "
			"-------------\n");
	p += sprintf(p, "                %sabled           "
			"              %sabled\n",
		(reg72&0x80)?"dis":" en",
		(reg7a&0x80)?"dis":" en");
	p += sprintf(p, "--------------- drive0 "
		"--------- drive1 -------- drive0 "
		"---------- drive1 ------\n");
	p += sprintf(p, "DMA enabled:    %s              %s"
			"             %s               %s\n",
		(reg72&0x20)?"yes":"no ", (reg72&0x40)?"yes":"no ",
		(reg7a&0x20)?"yes":"no ", (reg7a&0x40)?"yes":"no ");

	p += sprintf(p, "DMA Mode:       %s(%s)          %s(%s)",
		(reg72&0x20)?((reg73&0x01)?"UDMA":" DMA"):" PIO",
		(reg72&0x20)?(
			((reg73&0x30)==0x30)?(((reg73&0x35)==0x35)?"3":"0"):
			((reg73&0x20)==0x20)?(((reg73&0x25)==0x25)?"3":"1"):
			((reg73&0x10)==0x10)?(((reg73&0x15)==0x15)?"4":"2"):
			((reg73&0x00)==0x00)?(((reg73&0x05)==0x05)?"5":"2"):
			"X"):"?",
		(reg72&0x40)?((reg73&0x02)?"UDMA":" DMA"):" PIO",
		(reg72&0x40)?(
			((reg73&0xC0)==0xC0)?(((reg73&0xC5)==0xC5)?"3":"0"):
			((reg73&0x80)==0x80)?(((reg73&0x85)==0x85)?"3":"1"):
			((reg73&0x40)==0x40)?(((reg73&0x4A)==0x4A)?"4":"2"):
			((reg73&0x00)==0x00)?(((reg73&0x0A)==0x0A)?"5":"2"):
			"X"):"?");
	p += sprintf(p, "         %s(%s)           %s(%s)\n",
		(reg7a&0x20)?((reg7b&0x01)?"UDMA":" DMA"):" PIO",
		(reg7a&0x20)?(
			((reg7b&0x30)==0x30)?(((reg7b&0x35)==0x35)?"3":"0"):
			((reg7b&0x20)==0x20)?(((reg7b&0x25)==0x25)?"3":"1"):
			((reg7b&0x10)==0x10)?(((reg7b&0x15)==0x15)?"4":"2"):
			((reg7b&0x00)==0x00)?(((reg7b&0x05)==0x05)?"5":"2"):
			"X"):"?",
		(reg7a&0x40)?((reg7b&0x02)?"UDMA":" DMA"):" PIO",
		(reg7a&0x40)?(
			((reg7b&0xC0)==0xC0)?(((reg7b&0xC5)==0xC5)?"3":"0"):
			((reg7b&0x80)==0x80)?(((reg7b&0x85)==0x85)?"3":"1"):
			((reg7b&0x40)==0x40)?(((reg7b&0x4A)==0x4A)?"4":"2"):
			((reg7b&0x00)==0x00)?(((reg7b&0x0A)==0x0A)?"5":"2"):
			"X"):"?" );
	p += sprintf(p, "PIO Mode:       %s                %s"
			"               %s                 %s\n",
			"?", "?", "?", "?");
	p += sprintf(p, "                %s                     %s\n",
		(reg50 & CFR_INTR_CH0) ? "interrupting" : "polling     ",
		(reg57 & ARTTIM23_INTR_CH1) ? "interrupting" : "polling");
	p += sprintf(p, "                %s                          %s\n",
		(reg71 & MRDMODE_INTR_CH0) ? "pending" : "clear  ",
		(reg71 & MRDMODE_INTR_CH1) ? "pending" : "clear");
	p += sprintf(p, "                %s                          %s\n",
		(reg71 & MRDMODE_BLK_CH0) ? "blocked" : "enabled",
		(reg71 & MRDMODE_BLK_CH1) ? "blocked" : "enabled");

#ifdef DEBUG_CMD_REGS
	SPLIT_BYTE(reg50, hi_byte, lo_byte);
	p += sprintf(p, "CFR       = 0x%02x, HI = 0x%02x, "
			"LOW = 0x%02x\n", reg50, hi_byte, lo_byte);
	SPLIT_BYTE(reg57, hi_byte, lo_byte);
	p += sprintf(p, "ARTTIM23  = 0x%02x, HI = 0x%02x, "
			"LOW = 0x%02x\n", reg57, hi_byte, lo_byte);
	SPLIT_BYTE(reg71, hi_byte, lo_byte);
	p += sprintf(p, "MRDMODE   = 0x%02x, HI = 0x%02x, "
			"LOW = 0x%02x\n", reg71, hi_byte, lo_byte);
#endif /* DEBUG_CMD_REGS */

	return (char *)p;
}

static int cmd64x_get_info (char *buffer, char **addr, off_t offset, int count)
{
	char *p = buffer;
	int i;

	p += sprintf(p, "\n");
	for (i = 0; i < n_cmd_devs; i++) {
		struct pci_dev *dev	= cmd_devs[i];
		p = print_cmd64x_get_info(p, dev, i);
	}
	return p-buffer;	/* => must be less than 4k! */
}

#endif	/* defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS) */

/*
 * Registers and masks for easy access by drive index:
 */
#if 0
static u8 prefetch_regs[4]  = {CNTRL, CNTRL, ARTTIM23, ARTTIM23};
static u8 prefetch_masks[4] = {CNTRL_DIS_RA0, CNTRL_DIS_RA1, ARTTIM23_DIS_RA2, ARTTIM23_DIS_RA3};
#endif

/*
 * This routine writes the prepared setup/active/recovery counts
 * for a drive into the cmd646 chipset registers to active them.
 */
static void program_drive_counts (ide_drive_t *drive, int setup_count, int active_count, int recovery_count)
{
	unsigned long flags;
	struct pci_dev *dev = HWIF(drive)->pci_dev;
	ide_drive_t *drives = HWIF(drive)->drives;
	u8 temp_b;
	static const u8 setup_counts[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
	static const u8 recovery_counts[] =
		{15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
	static const u8 arttim_regs[2][2] = {
			{ ARTTIM0, ARTTIM1 },
			{ ARTTIM23, ARTTIM23 }
		};
	static const u8 drwtim_regs[2][2] = {
			{ DRWTIM0, DRWTIM1 },
			{ DRWTIM2, DRWTIM3 }
		};
	int channel = (int) HWIF(drive)->channel;
	int slave = (drives != drive);  /* Is this really the best way to determine this?? */

	cmdprintk("program_drive_count parameters = s(%d),a(%d),r(%d),p(%d)\n",
		setup_count, active_count, recovery_count, drive->present);
	/*
	 * Set up address setup count registers.
	 * Primary interface has individual count/timing registers for
	 * each drive.  Secondary interface has one common set of registers,
	 * for address setup so we merge these timings, using the slowest
	 * value.
	 */
	if (channel) {
		drive->drive_data = setup_count;
		setup_count = IDE_MAX(drives[0].drive_data,
					drives[1].drive_data);
		cmdprintk("Secondary interface, setup_count = %d\n",
					setup_count);
	}

	/*
	 * Convert values to internal chipset representation
	 */
	setup_count = (setup_count > 5) ? 0xc0 : (int) setup_counts[setup_count];
	active_count &= 0xf; /* Remember, max value is 16 */
	recovery_count = (int) recovery_counts[recovery_count];

	cmdprintk("Final values = %d,%d,%d\n",
		setup_count, active_count, recovery_count);

	/*
	 * Now that everything is ready, program the new timings
	 */
	local_irq_save(flags);
	/*
	 * Program the address_setup clocks into ARTTIM reg,
	 * and then the active/recovery counts into the DRWTIM reg
	 */
	(void) pci_read_config_byte(dev, arttim_regs[channel][slave], &temp_b);
	(void) pci_write_config_byte(dev, arttim_regs[channel][slave],
		((u8) setup_count) | (temp_b & 0x3f));
	(void) pci_write_config_byte(dev, drwtim_regs[channel][slave],
		(u8) ((active_count << 4) | recovery_count));
	cmdprintk ("Write %x to %x\n",
		((u8) setup_count) | (temp_b & 0x3f),
		arttim_regs[channel][slave]);
	cmdprintk ("Write %x to %x\n",
		(u8) ((active_count << 4) | recovery_count),
		drwtim_regs[channel][slave]);
	local_irq_restore(flags);
}

/*
 * Attempts to set the interface PIO mode.
 * The preferred method of selecting PIO modes (e.g. mode 4) is 
 * "echo 'piomode:4' > /proc/ide/hdx/settings".  Special cases are
 * 8: prefetch off, 9: prefetch on, 255: auto-select best mode.
 * Called with 255 at boot time.
 */

static void cmd64x_tuneproc (ide_drive_t *drive, u8 mode_wanted)
{
	int setup_time, active_time, recovery_time;
	int clock_time, pio_mode, cycle_time;
	u8 recovery_count2, cycle_count;
	int setup_count, active_count, recovery_count;
	int bus_speed = system_bus_clock();
	/*byte b;*/
	ide_pio_data_t  d;

	switch (mode_wanted) {
		case 8: /* set prefetch off */
		case 9: /* set prefetch on */
			mode_wanted &= 1;
			/*set_prefetch_mode(index, mode_wanted);*/
			cmdprintk("%s: %sabled cmd640 prefetch\n",
				drive->name, mode_wanted ? "en" : "dis");
			return;
	}

	mode_wanted = ide_get_best_pio_mode (drive, mode_wanted, 5, &d);
	pio_mode = d.pio_mode;
	cycle_time = d.cycle_time;

	/*
	 * I copied all this complicated stuff from cmd640.c and made a few
	 * minor changes.  For now I am just going to pray that it is correct.
	 */
	if (pio_mode > 5)
		pio_mode = 5;
	setup_time  = ide_pio_timings[pio_mode].setup_time;
	active_time = ide_pio_timings[pio_mode].active_time;
	recovery_time = cycle_time - (setup_time + active_time);
	clock_time = 1000 / bus_speed;
	cycle_count = (cycle_time + clock_time - 1) / clock_time;

	setup_count = (setup_time + clock_time - 1) / clock_time;

	active_count = (active_time + clock_time - 1) / clock_time;

	recovery_count = (recovery_time + clock_time - 1) / clock_time;
	recovery_count2 = cycle_count - (setup_count + active_count);
	if (recovery_count2 > recovery_count)
		recovery_count = recovery_count2;
	if (recovery_count > 16) {
		active_count += recovery_count - 16;
		recovery_count = 16;
	}
	if (active_count > 16)
		active_count = 16; /* maximum allowed by cmd646 */

	/*
	 * In a perfect world, we might set the drive pio mode here
	 * (using WIN_SETFEATURE) before continuing.
	 *
	 * But we do not, because:
	 *	1) this is the wrong place to do it
	 *		(proper is do_special() in ide.c)
	 * 	2) in practice this is rarely, if ever, necessary
	 */
	program_drive_counts (drive, setup_count, active_count, recovery_count);

	cmdprintk("%s: selected cmd646 PIO mode%d : %d (%dns)%s, "
		"clocks=%d/%d/%d\n",
		drive->name, pio_mode, mode_wanted, cycle_time,
		d.overridden ? " (overriding vendor mode)" : "",
		setup_count, active_count, recovery_count);
}

static u8 cmd64x_ratemask (ide_drive_t *drive)
{
	struct pci_dev *dev	= HWIF(drive)->pci_dev;
	u8 mode = 0;

	switch(dev->device) {
		case PCI_DEVICE_ID_CMD_649:
			mode = 3;
			break;
		case PCI_DEVICE_ID_CMD_648:
			mode = 2;
			break;
		case PCI_DEVICE_ID_CMD_643:
			return 0;

		case PCI_DEVICE_ID_CMD_646:
		{
			unsigned int class_rev	= 0;
			pci_read_config_dword(dev,
				PCI_CLASS_REVISION, &class_rev);
			class_rev &= 0xff;
		/*
		 * UltraDMA only supported on PCI646U and PCI646U2, which
		 * correspond to revisions 0x03, 0x05 and 0x07 respectively.
		 * Actually, although the CMD tech support people won't
		 * tell me the details, the 0x03 revision cannot support
		 * UDMA correctly without hardware modifications, and even
		 * then it only works with Quantum disks due to some
		 * hold time assumptions in the 646U part which are fixed
		 * in the 646U2.
		 *
		 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
		 */
			switch(class_rev) {
				case 0x07:
				case 0x05:
					return 1;
				case 0x03:
				case 0x01:
				default:
					return 0;
			}
		}
	}
	if (!eighty_ninty_three(drive))
		mode = min(mode, (u8)1);
	return mode;
}

static void config_cmd64x_chipset_for_pio (ide_drive_t *drive, u8 set_speed)
{
	u8 speed	= 0x00;
	u8 set_pio	= ide_get_best_pio_mode(drive, 4, 5, NULL);

	cmd64x_tuneproc(drive, set_pio);
	speed = XFER_PIO_0 + set_pio;
	if (set_speed)
		(void) ide_config_drive_speed(drive, speed);
}

static void config_chipset_for_pio (ide_drive_t *drive, u8 set_speed)
{
	config_cmd64x_chipset_for_pio(drive, set_speed);
}

static int cmd64x_tune_chipset (ide_drive_t *drive, u8 xferspeed)
{
	ide_hwif_t *hwif	= HWIF(drive);
	struct pci_dev *dev	= hwif->pci_dev;

	u8 unit			= (drive->select.b.unit & 0x01);
	u8 regU = 0, pciU	= (hwif->channel) ? UDIDETCR1 : UDIDETCR0;
	u8 regD = 0, pciD	= (hwif->channel) ? BMIDESR1 : BMIDESR0;

	u8 speed	= ide_rate_filter(cmd64x_ratemask(drive), xferspeed);

	if (speed > XFER_PIO_4) {
		(void) pci_read_config_byte(dev, pciD, &regD);
		(void) pci_read_config_byte(dev, pciU, &regU);
		regD &= ~(unit ? 0x40 : 0x20);
		regU &= ~(unit ? 0xCA : 0x35);
		(void) pci_write_config_byte(dev, pciD, regD);