📄 debouncing.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library altera;
use altera.maxplus2.all;
--
--***********************
entity debouncing is
port
(
d_in,clk: in std_logic;
d_out: out std_logic
);
end debouncing;
architecture de of debouncing is
signal vcc,inv_d: std_logic;
signal d1,d0,q1,q0: std_logic;
begin
vcc <= '1';
inv_d <= not d_in;
dff1: dff port map(d => d_in,q => q0,clk => clk,clrn => vcc,prn => vcc);
dff2: dff port map(d => q0,q => q1,clk => clk,clrn => vcc,prn => vcc);
process(clk)
begin
if (clk'event and clk='1') then
if(q0='1' and q1='1') then
d_out <= '1';
elsif(q0='0' and q1='0') then
d_out<='0';
end if;
end if;
end process;
end de;
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