📄 keyboard.rpt
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_X015 = EXP(!_LC034 & _LC038 & _LC045 & _LC059 & q4);
_X016 = EXP( _LC034 & _LC038 & _LC045 & !_LC059);
-- Node name is 'g' = 'yout0'
-- Equation name is 'g', location is LC051, type is output.
g = DFFE( _EQ011 $ VCC, clk_debounce, VCC, VCC, VCC);
_EQ011 = _X001 & _X007 & _X013 & _X017 & _X018 & _X019 & _X020;
_X001 = EXP( _LC034 & !_LC038 & _LC045 & _LC059 & q4 & !q5);
_X007 = EXP(!_LC034 & _LC038 & _LC045 & _LC059);
_X013 = EXP( _LC034 & _LC038 & !_LC045 & _LC059 & q5);
_X017 = EXP( _LC034 & _LC038 & _LC045 & !_LC059 & q4 & !q5);
_X018 = EXP( _LC034 & _LC038 & _LC045 & !_LC059 & !q4 & q5);
_X019 = EXP( _LC034 & _LC038 & !_LC045 & _LC059 & !q4 & !q5);
_X020 = EXP( _LC034 & !_LC038 & _LC045 & _LC059 & q5);
-- Node name is 'out_numb0' = 'n0'
-- Equation name is 'out_numb0', location is LC037, type is output.
out_numb0 = TFFE( _EQ012, clk_debounce, VCC, VCC, VCC);
_EQ012 = !_LC034 & _LC038 & _LC045 & _LC059 & out_numb0
# _LC034 & _LC038 & _LC045 & !_LC059 & out_numb0
# _LC034 & !_LC038 & _LC045 & _LC059 & !out_numb0
# _LC034 & _LC038 & !_LC045 & _LC059 & !out_numb0;
-- Node name is 'out_numb1' = 'n1'
-- Equation name is 'out_numb1', location is LC036, type is output.
out_numb1 = TFFE( _EQ013, clk_debounce, VCC, VCC, VCC);
_EQ013 = _LC034 & !_LC038 & _LC045 & _LC059 & out_numb1
# _LC034 & _LC038 & _LC045 & !_LC059 & out_numb1
# !_LC034 & _LC038 & _LC045 & _LC059 & !out_numb1
# _LC034 & _LC038 & !_LC045 & _LC059 & !out_numb1;
-- Node name is 'out_numb2' = 'n2'
-- Equation name is 'out_numb2', location is LC049, type is output.
out_numb2 = TFFE(!_EQ014, clk_debounce, VCC, VCC, VCC);
_EQ014 = !_LC056 & _X021 & _X022 & _X023;
_X021 = EXP(!_LC034 & _LC038 & _LC045 & _LC059 & out_numb2 & !q4);
_X022 = EXP( _LC034 & _LC038 & _LC045 & !_LC059 & out_numb2 & !q4);
_X023 = EXP( _LC034 & _LC038 & !_LC045 & _LC059 & out_numb2 & !q4);
-- Node name is 'out_numb3' = 'n3'
-- Equation name is 'out_numb3', location is LC035, type is output.
out_numb3 = TFFE(!_EQ015, clk_debounce, VCC, VCC, VCC);
_EQ015 = !_LC039 & _X024 & _X025 & _X026;
_X024 = EXP(!_LC034 & _LC038 & _LC045 & _LC059 & out_numb3 & !q5);
_X025 = EXP( _LC034 & _LC038 & _LC045 & !_LC059 & out_numb3 & !q5);
_X026 = EXP( _LC034 & _LC038 & !_LC045 & _LC059 & out_numb3 & !q5);
-- Node name is ':40' = 'q1'
-- Equation name is 'q1', location is LC055, type is buried.
q1 = TFFE( clk_debounce, GLOBAL( clk_4M), VCC, VCC, VCC);
-- Node name is ':39' = 'q2'
-- Equation name is 'q2', location is LC054, type is buried.
q2 = TFFE( _EQ016, GLOBAL( clk_4M), VCC, VCC, VCC);
_EQ016 = clk_debounce & q1;
-- Node name is ':38' = 'q3'
-- Equation name is 'q3', location is LC060, type is buried.
q3 = TFFE( _EQ017, GLOBAL( clk_4M), VCC, VCC, VCC);
_EQ017 = clk_debounce & q1 & q2;
-- Node name is ':37' = 'q4'
-- Equation name is 'q4', location is LC061, type is buried.
q4 = TFFE( _EQ018, GLOBAL( clk_4M), VCC, VCC, VCC);
_EQ018 = clk_debounce & q1 & q2 & q3;
-- Node name is ':36' = 'q5'
-- Equation name is 'q5', location is LC050, type is buried.
q5 = TFFE( _EQ019, GLOBAL( clk_4M), VCC, VCC, VCC);
_EQ019 = clk_debounce & q1 & q2 & q3 & q4;
-- Node name is '|debouncing:u1|dff1'
-- Equation name is '_LC047', type is buried
_LC047 = DFFE( key_in0 $ GND, clk_debounce, VCC, VCC, VCC);
-- Node name is '|debouncing:u1|dff2'
-- Equation name is '_LC063', type is buried
_LC063 = DFFE( _LC047 $ GND, clk_debounce, VCC, VCC, VCC);
-- Node name is '|debouncing:u1|:3'
-- Equation name is '_LC059', type is buried
_LC059 = DFFE( _EQ020 $ _LC047, clk_debounce, VCC, VCC, VCC);
_EQ020 = !_LC047 & _LC059 & _LC063
# _LC047 & !_LC059 & !_LC063;
-- Node name is '|debouncing:u2|dff1'
-- Equation name is '_LC043', type is buried
_LC043 = DFFE( key_in1 $ GND, clk_debounce, VCC, VCC, VCC);
-- Node name is '|debouncing:u2|dff2'
-- Equation name is '_LC044', type is buried
_LC044 = DFFE( _LC043 $ GND, clk_debounce, VCC, VCC, VCC);
-- Node name is '|debouncing:u2|:3'
-- Equation name is '_LC038', type is buried
_LC038 = DFFE( _EQ021 $ _LC043, clk_debounce, VCC, VCC, VCC);
_EQ021 = _LC038 & !_LC043 & _LC044
# !_LC038 & _LC043 & !_LC044;
-- Node name is '|debouncing:u3|dff1'
-- Equation name is '_LC027', type is buried
_LC027 = DFFE( key_in2 $ GND, clk_debounce, VCC, VCC, VCC);
-- Node name is '|debouncing:u3|dff2'
-- Equation name is '_LC048', type is buried
_LC048 = DFFE( _LC027 $ GND, clk_debounce, VCC, VCC, VCC);
-- Node name is '|debouncing:u3|:3'
-- Equation name is '_LC034', type is buried
_LC034 = DFFE( _EQ022 $ _LC027, clk_debounce, VCC, VCC, VCC);
_EQ022 = !_LC027 & _LC034 & _LC048
# _LC027 & !_LC034 & !_LC048;
-- Node name is '|debouncing:u4|dff1'
-- Equation name is '_LC017', type is buried
_LC017 = DFFE( key_in3 $ GND, clk_debounce, VCC, VCC, VCC);
-- Node name is '|debouncing:u4|dff2'
-- Equation name is '_LC042', type is buried
_LC042 = DFFE( _LC017 $ GND, clk_debounce, VCC, VCC, VCC);
-- Node name is '|debouncing:u4|:3'
-- Equation name is '_LC045', type is buried
_LC045 = DFFE( _EQ023 $ _LC017, clk_debounce, VCC, VCC, VCC);
_EQ023 = !_LC017 & _LC042 & _LC045
# _LC017 & !_LC042 & !_LC045;
-- Node name is '~1814~1'
-- Equation name is '~1814~1', location is LC039, type is buried.
-- synthesized logic cell
_LC039 = LCELL( _EQ024 $ GND);
_EQ024 = _LC034 & _LC038 & !_LC045 & _LC059 & !out_numb3 & q5
# !_LC034 & _LC038 & _LC045 & _LC059 & !out_numb3 & q5
# _LC034 & !_LC038 & _LC045 & _LC059 & !out_numb3 & q5
# _LC034 & _LC038 & _LC045 & !_LC059 & !out_numb3 & q5
# _LC034 & !_LC038 & _LC045 & _LC059 & out_numb3 & !q5;
-- Node name is '~1820~1'
-- Equation name is '~1820~1', location is LC056, type is buried.
-- synthesized logic cell
_LC056 = LCELL( _EQ025 $ GND);
_EQ025 = _LC034 & _LC038 & !_LC045 & _LC059 & !out_numb2 & q4
# !_LC034 & _LC038 & _LC045 & _LC059 & !out_numb2 & q4
# _LC034 & !_LC038 & _LC045 & _LC059 & !out_numb2 & q4
# _LC034 & _LC038 & _LC045 & !_LC059 & !out_numb2 & q4
# _LC034 & !_LC038 & _LC045 & _LC059 & out_numb2 & !q4;
-- Node name is '~1850~1'
-- Equation name is '~1850~1', location is LC058, type is buried.
-- synthesized logic cell
_LC058 = LCELL( _EQ026 $ GND);
_EQ026 = _LC038 & _LC045 & _LC059 & !q4 & !q5
# _LC034 & _LC045 & _LC059
# _LC038 & q4 & q5
# !_LC034 & _LC038 & !_LC059
# !_LC034 & _LC038 & !_LC045;
-- Shareable expanders that are duplicated in multiple LABs:
-- _X001 occurs in LABs B, C, D
-- _X002 occurs in LABs B, C
-- _X007 occurs in LABs B, D
-- _X008 occurs in LABs C, D
-- _X013 occurs in LABs C, D
Project Information e:\study\homework\vhdl program\keyboard.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:02
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,415K
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