atm.vhd

atm信元检测

LIBRARY IEEE;        
USE     IEEE.Std_Logic_1164.ALL;
USE     IEEE.std_logic_unsigned.all;
USE     IEEE.std_logic_arith.all;

entity atm is
    port(
--        my_clk:   in std_logic;
--        rst:   in std_logic;
        s:     out std_logic_vector(2 downto 0)
        );
end atm;

use work.all;
architecture rtl of atm is

signal clk:   std_logic := '1';
--constant t_pw : time := 50ns;
signal rst:   std_logic;
signal send_bit:       std_logic;
--signal counter:       integer range 0 to 150000;
--signal counter2:	 integer range 0 to 500;
--signal clk:  std_logic; 
--signal aa:   std_logic;
signal output_flag:  std_logic;
signal cell_output:  std_logic_vector(39 downto 0);

    
component sender
    port(
        clk:           in  std_logic;
        rst:           in  std_logic;
        send_bit:      out std_logic);
end component;

component receiver
    port(
        clk:      in std_logic;
        rst:           in  std_logic;
        send_bit:      in std_logic;
        output_flag:  out std_logic;
        cell_output:  out std_logic_vector(39 downto 0);        
        s:             out std_logic_vector(2 downto 0)
        );
end component;        
   
begin
    atm_sender:sender port map(clk,rst,send_bit);
    atm_receiver:receiver port map(clk,rst,send_bit,output_flag,cell_output,s);
--    process(rst)
--    begin
--    if(rst = '0') then
--       counter <= 0;
--       clk <= '1';
--    else
--       if(my_clk'event and my_clk='1') then
--          if(counter<150000) then
--             counter<= counter+1;
--          else
--             counter <= 1;
--             clk<= not clk;
--          end if;
--       end if;
--    end if;
--    end process;
    
    clock_gen : process(clk)
    begin
        clk <= not clk after 50ns;
    end process clock_gen; 
    
    
    rst<='0','1' after 10ns;
end rtl;