receiver.vhd

atm信元检测

LIBRARY IEEE;        
USE     IEEE.Std_Logic_1164.ALL;
USE     IEEE.std_logic_unsigned.all;
USE     IEEE.std_logic_arith.all;

entity receiver is
    port(
        clk:   in std_logic;
        rst:   in std_logic;
        send_bit:   in std_logic;
        output_flag:  out std_logic;
        cell_output:  out std_logic_vector(39 downto 0);
        s:    out std_logic_vector(2 downto 0)        
        );
end receiver;

use work.all;
architecture rtl of receiver is

signal one_err:        std_logic;    
signal multi_err:      std_logic;
signal check_sig:      std_logic;
signal header_output:  std_logic_vector(39 downto 0); 
signal rec_state:      std_logic_vector(2 downto 0);
signal syn_counter:    integer range 0 to 3;
signal rec_counter:    integer range 0 to 424;
signal dec_counter:    integer range 0 to 40;
signal flag:           std_logic;
signal header_f:       std_logic;
signal crc_f:          std_logic;
signal beta:         integer range 0 to 5;
signal alpha:        integer range 0 to 5;
    
component decoder is
port(
    clk:           in  std_logic;
    rst:           in  std_logic;
    header_f:   in  std_logic;
    crc_f:      in  std_logic;
    send_bit:      in std_logic;
    rec_state:     in std_logic_vector(2 downto 0);
    dec_counter:   in integer range 0 to 40;
    one_err:       out std_logic;    
    multi_err:     out std_logic;
    check_sig:     out std_logic;
    flag:          out std_logic;
    header_output: out std_logic_vector(39 downto 0)    
    );
end component;

begin
    atm_decoder:decoder port map(clk,rst,header_f,crc_f,send_bit,rec_state,dec_counter,one_err,multi_err,check_sig,flag,header_output);        
    
    s <= rec_state;                                                  
                                                       
    process(clk,rst,one_err,multi_err,check_sig,rec_state,rec_counter,syn_counter,dec_counter)
    begin
        if(rst='0') then
            rec_state <= "000";
            output_flag <= '0';
            cell_output <= x"0000000000";
            syn_counter <= 1;
            rec_counter <= 0;
            header_f <= '0';
            crc_f <= '0';
        else
            if(clk'event and clk='1') then
                if(syn_counter=1) then
                    syn_counter <= 2;
                else if(syn_counter=2) then
                         syn_counter <= 0;
                         header_f <= '1';
                         crc_f <= '1';
                         rec_counter <= 1;
                         dec_counter <= 0;
                     end if;
                end if;
                case rec_state is
                    when "000" =>
                        if(syn_counter=0) then
                            header_f <= '1';
                            crc_f <= '1';
                            if(dec_counter<40) then
                                dec_counter <= dec_counter+1;
                            else
                                null;
                            end if;
                            if(flag='1') then
                                rec_state <= "001";
                                dec_counter <= 0;
                                rec_counter <= 43;
                                header_f <= '0';
                                crc_f <= '0';
                                beta <= beta+1;
                            else
                                rec_state <= "000";
                            end if;              
                        end if;
                    when "001" =>
                        case rec_counter is
                            when 32 =>
                                crc_f <= '1';
                                header_f <= '0';
                                rec_counter <= rec_counter+1;
                            when 40 =>
                                crc_f <= '0';
                                rec_counter <= rec_counter+1;
                            when 424 =>
                                rec_counter <= 1;
                                header_f <= '1';                                
                            when others =>
                                rec_counter <= rec_counter+1;
                        end case;
                        if(check_sig= '1') then
                            cell_output <= header_output;
                            if(multi_err='1') then
                                rec_state <= "000";
                                dec_counter <= 0;
                                beta <= 0;
                                rec_counter <= 43;
                                header_f <= '1';
                                crc_f <= '1'; 
                                output_flag <= '0';                               
                            else if(one_err= '1') then
                                     rec_state <= "101";
                                     beta <= 0;
                                     output_flag <= '0';
                                 else
                                     if(beta<2) then
                                         beta<=beta+1;
                                         output_flag <= '0';
                                     else
                                         beta<=0;
                                         rec_state <= "100";
                                         output_flag <= '1';
                                     end if;
                                 end if;
                            end if;
                        end if;
                    when "010" =>
                        case rec_counter is
                            when 32 =>
                                crc_f <= '1';
                                header_f <= '0';
                                rec_counter <= rec_counter+1;
                            when 40 =>
                                crc_f <= '0';
                                rec_counter <= rec_counter+1;
                            when 424 =>
                                rec_counter <= 1;
                                header_f<='1';                               
                            when others =>
                                rec_counter <= rec_counter+1;
                        end case;
                        if(check_sig= '1') then
                            cell_output <= header_output;
                            if(multi_err='1') then
                                rec_state <= "011";
                                alpha <= alpha +1;
                                output_flag <= '0';
                            else if(one_err= '1') then
                                     rec_state <= "010";
                                     output_flag <= '0';
                                 else
                                     rec_state <= "100";
                                     output_flag <= '1';
                                 end if;
                            end if;
                        end if;                                                
                    when "011" =>
                        case rec_counter is
                            when 32 =>
                                crc_f <= '1';
                                header_f <= '0';
                                rec_counter <= rec_counter+1;
                            when 40 =>
                                crc_f <= '0';
                                rec_counter <= rec_counter+1;
                            when 424 =>
                                rec_counter <= 1;
                                header_f <= '1';                                
                            when others =>
                                rec_counter <= rec_counter+1;
                        end case;
                        if(check_sig= '1') then
                            cell_output <= header_output;
                            if(multi_err='1' or one_err='1') then
                                if(alpha<2) then
                                    alpha <= alpha+1;
                                else
                                    rec_counter <= 43;
                                    rec_state <= "000";
                                    dec_counter <= 0;
                                    alpha <= 0;
                                    header_f <= '1';
                                    crc_f <= '1';                                     
                                end if;
                                output_flag <= '0';
                            else
                                rec_state <= "100";
                                alpha <= 0;
                                output_flag <= '1';
                            end if;
                        end if;                                                
                    when "100" =>
                        case rec_counter is
                            when 32 =>
                                crc_f <= '1';
                                header_f <= '0';
                                rec_counter <= rec_counter+1;
                            when 40 =>
                                crc_f <= '0';
                                rec_counter <= rec_counter+1;
                            when 424 =>
                                rec_counter <= 1;
                                header_f<='1';                                
                            when others =>
                                rec_counter <= rec_counter+1;
                        end case;                        
                        if(check_sig= '1') then
                            cell_output <= header_output;
                            if(multi_err='1') then
                                rec_state <= "011";
                                alpha <= alpha+1;
                                output_flag <= '0';
                            else if(one_err= '1') then
                                     rec_state <= "010";
                                 else
                                     rec_state <= "100";
                                 end if;
                                 output_flag <= '1';
                            end if;
                        end if;                                                
                    when "101" =>
                        case rec_counter is
                            when 32 =>
                                crc_f <= '1';
                                header_f <= '0';
                                rec_counter <= rec_counter+1;
                            when 40 =>
                                crc_f <= '0';
                                rec_counter <= rec_counter+1;
                            when 424 =>
                                rec_counter <= 1;
                                header_f<='1';                                
                            when others =>
                                rec_counter <= rec_counter+1;
                        end case;
                        if(check_sig= '1') then
                            output_flag <= '0';
                            if(multi_err='1') then
                                rec_state <= "000";
                                dec_counter <= 0;
                                rec_counter <= 43;
                                header_f <= '1';
                                crc_f <= '1';                                 
                            else if(one_err= '1') then
                                     rec_state <= "101";
                                 else
                                     rec_state <= "001";
                                     beta <= beta +1;
                                 end if;
                            end if;
                        end if;                        
                    when others =>
                        null;
                end case;
            end if;
        end if;
    end process;
end rtl;