decoder.vhd.bak

atm信元检测

LIBRARY IEEE;        
USE     IEEE.Std_Logic_1164.ALL;
USE     IEEE.std_logic_unsigned.all;
USE     IEEE.std_logic_arith.all;

entity decoder is
port(
    clk:           in  std_logic;
    rst:           in  std_logic;
    header_f:   in  std_logic;
    crc_f:      in  std_logic;
    send_bit:      in std_logic;
    rec_state:     in std_logic_vector(2 downto 0);
    dec_counter:   in integer range 0 to 40;
    one_err:       out std_logic;    
    multi_err:     out std_logic;
    check_sig:     out std_logic;
    flag:          out std_logic;
    header_output: out std_logic_vector(39 downto 0)     
    );
end decoder;

architecture behavior of decoder is
signal K_a:        std_logic;
signal K_b:        std_logic;
signal div_reg:    std_logic_vector(7 downto 0);
signal h_cache:    std_logic_vector(39 downto 0);
signal count:      integer range 0 to 424;
signal shift_c:    integer range 0 to 39;
signal shifter:    std_logic_vector(39 downto 0);
signal one_error:  std_logic;
signal multi_error: std_logic;
signal last_state: std_logic;
begin
    K_a <= send_bit when header_f='1' or crc_f='1' else
           '0';
    K_b <= shifter(39) when rec_state="000" else
           '0';
--    flag <= '1' when div_reg=x"00" and dec_counter=40 else
--            '0';
    header_output <= h_cache;
    one_err <= one_error;
    multi_err <= multi_error;            
    process(rst,clk,header_f,crc_f,send_bit,K_a,K_b,dec_counter)
    variable v_count:   integer range 0 to 424;
    begin
        if(rst='0') then
            div_reg <= x"00";
            h_cache <= x"0000000000";
            shifter <= x"0000000000";
            count <= 1;
            shift_c<= 0;
            check_sig <= '0';
            one_error <= '0';
            multi_error <= '0'; 
            last_state <= '0';
            flag <= '0';           
        else if(clk'event and clk='1') then
                 for shift_c in 39 downto 1 loop
                     shifter(shift_c) <= shifter(shift_c-1);
                 end loop;
                 shifter(0) <= send_bit;
                 div_reg(7) <= div_reg(6);
                 div_reg(6) <= div_reg(5) xor K_b;
                 div_reg(5) <= div_reg(4) xor K_b;
                 div_reg(4) <= div_reg(3);
                 div_reg(3) <= div_reg(2);
                 div_reg(2) <= div_reg(7) xor div_reg(1);
                 div_reg(1) <= div_reg(7) xor div_reg(0) xor K_b;
                 div_reg(0) <= K_a xor div_reg(7); 
                 if(div_reg = x"00" and dec_counter=40) then
                    flag <= '1';
                    count <= 42;
                    last_state <= '1';
                 else
                    flag <= '0';
                 end if; 
                 if(rec_state = "000") then
                    if(count > 80) then
                        count <= 1;
                        shifter <= x"0000000000";
                    else
                        null;
                    end if;
                 else
                    v_count := count;
                    if(v_count<424) then
                        v_count := v_count+1;                        
                    else
                        v_count := 1;
                        last_state <= '0';
                    end if;
                    if(v_count<=40 and v_count>0) then
                        h_cache(40-v_count) <= send_bit;
                    end if;                     
                    if(div_reg = "00110001" and v_count>40 and v_count<=80 and last_state='0') then
                        h_cache(80-v_count) <= h_cache(80-v_count) xor '1';
                        one_error <= '1';
                        multi_error <= '0';
                    else
                        null;
                    end if;  
                    if(v_count>80) then
                        div_reg <= x"00";
                        one_error <= '0';
                        multi_error <= '0';
                    else 
                        null;
                    end if;  
                    if(count=40) then
                        if(div_reg= x"00") then
                            multi_error <= '0';
                        else
                            multi_error <= '1';                            
                        end if;
                    else
                        null;
                    end if;
                    if(v_count=80 and last_state='0') then
                        check_sig <= '1';
                    else
                        check_sig <= '0';
                    end if; 
                    count <= v_count;           
                end if;
            end if;
        end if;  
    end process;
end behavior;