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LIBRARY IEEE; USE IEEE.Std_Logic_1164.ALL;USE IEEE.std_logic_unsigned.all;USE IEEE.std_logic_arith.all;entity sender is port( clk: in std_logic; rst: in std_logic; send_bit: out std_logic );end sender;use work.all;architecture rtl of sender istype noise_additive is array(0 to 63) of std_logic_vector(0 to 39);signal header: std_logic_vector(39 downto 0);signal data: std_logic_vector(383 downto 0);signal header_flag: std_logic;signal info_bit: std_logic;signal crc_flag: std_logic;signal code_bit: std_logic;signal counter: integer range 0 to 424;signal period: integer range 0 to 64;signal noise: noise_additive;signal noise_bit: std_logic; component encoder port( clk: in std_logic; rst: in std_logic; header_flag: in std_logic; info_bit: in std_logic; crc_flag: in std_logic; code_bit: out std_logic);end component; begin atm_encoder:encoder port map(clk,rst,header_flag,info_bit,crc_flag,code_bit); send_bit <= code_bit xor noise_bit;-- send_bit <= code_bit; process(clk,rst,counter,period) variable counter_v: integer range 0 to 424; begin counter_v := counter; if(rst='0') then header <= x"A423F27900"; data <= x"111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111"; header_flag <= '0'; info_bit <= '0'; crc_flag <= '0'; counter <= 315; period <= 0; noise_bit <= '0'; noise(0) <= x"0000000000"; noise(1) <= x"0000000000"; noise(2) <= x"0000000000"; noise(3) <= x"1000000000"; noise(4) <= x"0400000000"; noise(5) <= x"0000000000"; noise(6) <= x"0000000000"; noise(7) <= x"0000000000"; noise(8) <= x"0000000000"; noise(9) <= x"0001000000"; noise(10) <= x"0000000001"; noise(11) <= x"0000000000"; noise(12) <= x"0010010000"; noise(13) <= x"0000100000"; noise(14) <= x"0000000000"; noise(15) <= x"0001000000"; noise(16) <= x"0000001000"; noise(17) <= x"0100010000"; noise(18) <= x"0010000100"; noise(19) <= x"1000000000"; noise(20) <= x"0000000000"; noise(21) <= x"0000000000"; noise(22) <= x"0000000000"; noise(23) <= x"0000000000"; noise(24) <= x"0700000000"; noise(25) <= x"0005000000"; noise(26) <= x"0000000007"; noise(27) <= x"0000000000"; noise(28) <= x"1000000000"; noise(29) <= x"0050000000"; noise(30) <= x"0000000000"; noise(31) <= x"7000000000"; noise(32) <= x"0000000000"; noise(33) <= x"0000000000"; noise(34) <= x"0000000000"; noise(35) <= x"0000000000"; noise(36) <= x"0000000000"; noise(37) <= x"0000000000"; noise(38) <= x"0000000000"; noise(39) <= x"0000000000"; noise(40) <= x"0000000000"; noise(41) <= x"0000000000"; noise(42) <= x"0000000000"; noise(43) <= x"0000000000"; noise(44) <= x"0000000000"; noise(45) <= x"0000000000"; noise(46) <= x"0000000000"; noise(47) <= x"0000000000"; noise(48) <= x"0000000000"; noise(49) <= x"0000000000"; noise(50) <= x"0000000000"; noise(51) <= x"0000000000"; noise(52) <= x"0000000000"; noise(53) <= x"0000000000"; noise(54) <= x"0000000000"; noise(55) <= x"0000000000"; noise(56) <= x"0000000000"; noise(57) <= x"0000000000"; noise(58) <= x"0000000000"; noise(59) <= x"0000000000"; noise(60) <= x"0000000000"; noise(61) <= x"0000000000"; noise(62) <= x"0000000000"; noise(63) <= x"0000000000"; else if(clk'event and clk='1') then if(counter_v=424) then counter_v:=1; if(period=63) then period <= 0; else period <= period +1; end if; else counter_v := counter_v+1; end if; counter <= counter_v; if(counter_v<=40) then info_bit <= header(40-counter_v); else info_bit <= data(384-counter_v+40); end if; if(counter_v=1) then header_flag <= '1'; else if(counter_v=33) then crc_flag <= '1'; header_flag <='0'; else if(counter_v=41) then crc_flag <= '0'; end if; end if; end if; if(counter_v<42 and counter_v>1) then noise_bit <= noise(period)(counter_v-2); else noise_bit <= '0'; end if; end if; end if; end process; end rtl;
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