encoder.vhd

atm信元检测

LIBRARY IEEE;        
USE     IEEE.Std_Logic_1164.ALL;
USE     IEEE.std_logic_unsigned.all;
USE     IEEE.std_logic_arith.all;

entity encoder is
port(
    clk:           in  std_logic;
    rst:           in  std_logic;
    header_flag:   in  std_logic;
    info_bit:      in  std_logic;
    crc_flag:      in  std_logic;
    code_bit:      out std_logic
    );
end encoder;

architecture behavior of encoder is
signal divide_reg:      std_logic_vector(7 downto 0);    
signal K_c:             std_logic := '0';
begin
    K_c <= info_bit xor divide_reg(7) when header_flag='1' else
           '0';
    process(rst,clk,crc_flag,K_c,divide_reg)
    begin
        if(rst='0') then
            divide_reg <= x"00";
            code_bit <= '0';
        else 
            if(clk'event and clk='1') then
                 if(crc_flag='1') then
                     code_bit <= divide_reg(7);
                 else
                     code_bit <= info_bit;
                 end if;
                 divide_reg(7) <= divide_reg(6);
                 divide_reg(6) <= divide_reg(5);
                 divide_reg(5) <= divide_reg(4);
                 divide_reg(4) <= divide_reg(3);
                 divide_reg(3) <= divide_reg(2);
                 divide_reg(2) <= K_c xor divide_reg(1);
                 divide_reg(1) <= K_c xor divide_reg(0);
                 divide_reg(0) <= K_c;
            end if;        
        end if;
    end process;
end behavior;