asm.txt

汇编用的MASM LINK DEBUG

@Assembler Programming Topics
:8086 architecture
^Intel 8086 Family Architecture

%	General Purpose Registers		Segment Registers

	AH/AL  AX  (EAX)  Accumulator		 CS	Code Segment
	BH/BL  BX  (EBX)  Base			 DS	Data Segment
	CH/CL  CX  (ECX)  Counter		 SS	Stack Segment
	DH/DL  DX  (EDX)  Data			 ES	Extra Segment
						(FS)	386 and newer
	(Exx) indicates 386+ 32 bit register 	(GS)	386 and newer


%	Pointer Registers			Stack Registers

	SI (ESI)  Source Index			SP (ESP)  Stack Pointer
	DI (EDI)  Destination Index		BP (EBP)  Base Pointer
	IP	  Instruction Pointer

%	Status Registers

	FLAGS Status Flags   (see ~FLAGS~)

%	Special Registers (386+ only)

	CR0	Control Register 0	  DR0	 Debug Register 0
	CR2	Control Register 2	  DR1	 Debug Register 1
	CR3	Control Register 3	  DR2	 Debug Register 2
					  DR3	 Debug Register 3
	TR4	Test Register 4		  DR6	 Debug Register 6
	TR5	Test Register 5		  DR7	 Debug Register 7
	TR6	Test Register 6
	TR7	Test Register 7
	
%	Register	  Default Segment    Valid Overrides

	BP			SS		DS, ES, CS
	SI or DI		DS		ES, SS, CS
	DI strings		ES		None
	SI strings		DS		ES, SS, CS


	- see  ~CPU~   ~DETECTING~  ~Instruction Timing~

:Instruction Timing
^Instruction Clock Cycle Calculation


	Some instructions require additional clock cycles due to a "Next
	Instruction Component" identified by a "+m" in the instruction
	clock cycle listings.  This is due to the prefetch queue being
	purge on a control transfers.	Below is the general rule for
	calculating "m":


	88/86 not applicable
	286  "m" is the number of bytes in the next instruction
	386  "m" is the number of components in the next instruction
		(the instruction coding (each byte), plus the data and
		the displacement are all considered components)


^8088/8086  Effective Address (EA) Calculation

%		   Description				  Clock Cycles

	Displacement						6
	Base or Index (BX,BP,SI,DI)				5
	Displacement+(Base or Index)				9
	Base+Index (BP+DI,BX+SI)				7
	Base+Index (BP+SI,BX+DI)				8
	Base+Index+Displacement (BP+DI,BX+SI)		       11
	Base+Index+Displacement (BP+SI+disp,BX+DI+disp)	       12


	- add 4 cycles for word operands at odd addresses
	- add 2 cycles for segment override
	- 80188/80186 timings differ from those of the 8088/8086/80286


%	Task State Calculation

	"TS" is defined as switching from VM/486 or 80286 TSS to one of
	the following:

 			谀哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪哪