📄 net_nic.c
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/*$PAGE*/
/* ---- MEMORY MANAGEMENT UNIT REGISTER (MMU) BITS ---- */
#define LAN91C111_REG_MMU_CMD_MASK 0x00E0
#define LAN91C111_REG_MMU_CMD_NOP 0x0000 /* No op. */
#define LAN91C111_REG_MMU_CMD_TX_ALLOC 0x0020 /* Req tx alloc. */
#define LAN91C111_REG_MMU_CMD_RESET 0x0040 /* Reset MMU. */
#define LAN91C111_REG_MMU_CMD_RX_REMOVE 0x0060 /* Remove rx frame from Rx FIFO. */
#define LAN91C111_REG_MMU_CMD_RX_REMOVE_REL 0x0080 /* Remove & rel rx frame from Rx FIFO. */
#define LAN91C111_REG_MMU_CMD_REL_PKT 0x00A0 /* Rel pkt. */
#define LAN91C111_REG_MMU_CMD_TX_PKT 0x00C0 /* Tx pkt. */
#define LAN91C111_REG_MMU_CMD_TX_RESET 0x00E0 /* Reset Tx FIFOs. */
#define LAN91C111_REG_MMD_CMD_TX_PG_SIZE 256 /* Backwards-compatible with LAN91C96. */
/* -------- PACKET NUMBER REGISTER (PNR) BITS --------- */
#define LAN91C111_REG_PNR_TX_PKT_NBR 0x003F /* Cur tx pkt nbr. */
#define LAN91C111_REG_PNR_TX_ALLOC_SHIFT 8
#define LAN91C111_REG_PNR_TX_ALLOC 0x3F00
#define LAN91C111_REG_PNR_TX_ALLOC_SUCCESS 0x0000 /* 0 : Tx alloc successful. */
#define LAN91C111_REG_PNR_TX_ALLOC_FAIL DEF_BIT_15 /* 1 : Tx alloc failed (dflt). */
/* --------- FIFO PORTS REGISTER (FIFO) BITS ---------- */
#define LAN91C111_REG_FIFO_RX_NOT_EMPTY DEF_BIT_NONE /* 0 : Rx FIFO NOT empty. */
#define LAN91C111_REG_FIFO_RX_EMPTY DEF_BIT_15 /* 1 : Rx FIFO empty (dflt). */
#define LAN91C111_REG_FIFO_RX_PKT_NBR 0x3F00
#define LAN91C111_REG_FIFO_TX_NOT_EMPTY DEF_BIT_NONE /* 0 : Tx FIFO NOT empty. */
#define LAN91C111_REG_FIFO_TX_EMPTY DEF_BIT_07 /* 1 : Tx FIFO empty (dflt). */
#define LAN91C111_REG_FIFO_TX_PKT_NBR 0x003F
/* ----------- POINTER REGISTER (PTR) BITS ------------ */
#define LAN91C111_REG_PTR_FIFO_TX DEF_BIT_NONE /* 0 : Tx FIFO Pkt Ptr. */
#define LAN91C111_REG_PTR_FIFO_RX DEF_BIT_15 /* 1 : Rx FIFO Pkt Ptr. */
#define LAN91C111_REG_PTR_INC_MAN DEF_BIT_NONE /* 0 : Manual ptr inc (dflt). */
#define LAN91C111_REG_PTR_INC_AUTO DEF_BIT_14 /* 1 : Auto ptr inc. */
#define LAN91C111_REG_PTR_WR DEF_BIT_NONE /* 0 : Wr. */
#define LAN91C111_REG_PTR_RD DEF_BIT_13 /* 1 : Rd. */
#define LAN91C111_REG_PTR_TX_UNDERRUN_DIS DEF_BIT_NONE /* 0 : Early Tx underrun detection DIS (dflt). */
#define LAN91C111_REG_PTR_TX_UNDERRUN_EN DEF_BIT_12 /* 1 : Early Tx underrun detection EN. */
#define LAN91C111_REG_PTR_WR_FIFO_EMPTY DEF_BIT_NONE /* 0 : Wr data FIFO empty (dflt). */
#define LAN91C111_REG_PTR_WR_FIFO_NOT_EMPTY DEF_BIT_11 /* 1 : Wr data FIFO NOT empty. */
#define LAN91C111_REG_PTR_PKT_IX 0x07FF
/*$PAGE*/
/* ------- INTERRUPT STATUS REGISTER (INT) BITS ------- */
#define LAN91C111_REG_INT_MASK_EN 0xFF00 /* Int En's mask. */
#define LAN91C111_REG_INT_MASK_STATUS 0x00FF /* Int status mask. */
#define LAN91C111_REG_INT_MD DEF_BIT_07 /* MD int status. */
#define LAN91C111_REG_INT_MD_ACK DEF_BIT_07 /* MD int ack. */
#define LAN91C111_REG_INT_MD_DIS DEF_BIT_NONE /* 0 : MD int DIS (dflt). */
#define LAN91C111_REG_INT_MD_EN DEF_BIT_15 /* 1 : MD int EN. */
#define LAN91C111_REG_INT_ERCV DEF_BIT_06 /* ERCV int status. */
#define LAN91C111_REG_INT_ERCV_ACK DEF_BIT_06 /* ERCV int ack. */
#define LAN91C111_REG_INT_ERCV_DIS DEF_BIT_NONE /* 0 : ERCV int DIS (dflt). */
#define LAN91C111_REG_INT_ERCV_EN DEF_BIT_14 /* 1 : ERCV int EN. */
#define LAN91C111_REG_INT_EPH DEF_BIT_05 /* EPH int status. */
#define LAN91C111_REG_INT_ERH_DIS DEF_BIT_NONE /* 0 : EPH int DIS (dflt). */
#define LAN91C111_REG_INT_ERH_EN DEF_BIT_13 /* 1 : EPH int EN. */
#define LAN91C111_REG_INT_RX_OVERRUN DEF_BIT_04 /* Rx Overrun int status. */
#define LAN91C111_REG_INT_RX_OVERRUN_ACK DEF_BIT_04 /* Rx Overrun int ack. */
#define LAN91C111_REG_INT_RX_OVERRUN_DIS DEF_BIT_NONE /* 0 : Rx Overrun int DIS (dflt). */
#define LAN91C111_REG_INT_RX_OVERRUN_EN DEF_BIT_12 /* 1 : Rx Overrun int EN. */
#define LAN91C111_REG_INT_TX_ALLOC DEF_BIT_03 /* Tx Alloc int status. */
#define LAN91C111_REG_INT_TX_ALLOC_DIS DEF_BIT_NONE /* 0 : Tx Alloc int DIS (dflt). */
#define LAN91C111_REG_INT_TX_ALLOC_EN DEF_BIT_11 /* 1 : Tx Alloc int EN. */
#define LAN91C111_REG_INT_TX_EMPTY DEF_BIT_02 /* Tx Empty int status. */
#define LAN91C111_REG_INT_TX_EMPTY_ACK DEF_BIT_02 /* Tx Empty int ack. */
#define LAN91C111_REG_INT_TX_EMPTY_DIS DEF_BIT_NONE /* 0 : Tx Empty int DIS (dflt). */
#define LAN91C111_REG_INT_TX_EMPTY_EN DEF_BIT_10 /* 1 : Tx Empty int EN. */
#define LAN91C111_REG_INT_TX DEF_BIT_01 /* Tx int status. */
#define LAN91C111_REG_INT_TX_ACK DEF_BIT_01 /* Tx int ack. */
#define LAN91C111_REG_INT_TX_DIS DEF_BIT_NONE /* 0 : Tx int DIS (dflt). */
#define LAN91C111_REG_INT_TX_EN DEF_BIT_09 /* 1 : Tx int EN. */
#define LAN91C111_REG_INT_RX DEF_BIT_00 /* Rx int status. */
#define LAN91C111_REG_INT_RX_DIS DEF_BIT_NONE /* 0 : Rx int DIS (dflt). */
#define LAN91C111_REG_INT_RX_EN DEF_BIT_08 /* 1 : Rx int EN. */
/* ---- MANAGEMENT INTERFACE REGISTER (MGMT) BITS ----- */
#define LAN91C111_REG_MGMT_MD_PHY_MASK 0x000F
#define LAN91C111_REG_MGMT_MD_OUT_DIS DEF_BIT_NONE /* 0 : MD output pin tri-stated (dflt). */
#define LAN91C111_REG_MGMT_MD_OUT_EN DEF_BIT_03 /* 1 : MD output pin follows MD output. */
#define LAN91C111_REG_MGMT_MD_CLK_LO DEF_BIT_NONE /* 0 : MD clk LO. */
#define LAN91C111_REG_MGMT_MD_CLK_HI DEF_BIT_02 /* 1 : MD clk HI. */
#define LAN91C111_REG_MGMT_MD_IN_LO DEF_BIT_NONE /* 0 : MD input LO. */
#define LAN91C111_REG_MGMT_MD_IN_HI DEF_BIT_01 /* 1 : MD input HI. */
#define LAN91C111_REG_MGMT_MD_OUT_LO DEF_BIT_NONE /* 0 : MD output LO. */
#define LAN91C111_REG_MGMT_MD_OUT_HI DEF_BIT_00 /* 1 : MD output HI. */
/*$PAGE*/
/*
*********************************************************************************************************
* LAN91C111 PHYSICAL (PHY) REGISTERS
*
* Note(s) : (1) See SMSC LAN91C111, Sections 9 - 9.10 for LAN91C111 Physical register summary.
*********************************************************************************************************
*/
/* --------------------- PHY REGS --------------------- */
#define LAN91C111_PHY_REG_CTRL 0
#define LAN91C111_PHY_REG_STATUS 1
#define LAN91C111_PHY_REG_ID_1 2
#define LAN91C111_PHY_REG_ID_2 3
#define LAN91C111_PHY_REG_AUTO_NEG_AD 4
#define LAN91C111_PHY_REG_AUTO_NEG_REM 5
#define LAN91C111_PHY_REG_CFG_1 16
#define LAN91C111_PHY_REG_CFG_2 17
#define LAN91C111_PHY_REG_STATUS_OUT 18
#define LAN91C111_PHY_REG_INT 19
#define LAN91C111_PHY_REG_RD 0
#define LAN91C111_PHY_REG_WR 1
#define LAN91C111_PHY_FRAME_IDLE_BIT_NBR 32
#define LAN91C111_PHY_FRAME_PHY_DEV_ADDR_BIT_NBR 5
#define LAN91C111_PHY_FRAME_PHY_REG_BIT_NBR 5
#define LAN91C111_PHY_FRAME_DATA_BIT_NBR 16
/*
*********************************************************************************************************
* LAN91C111 PHYSICAL (PHY) REGISTER BITS
*********************************************************************************************************
*/
/* -- PHYSICAL CONTROL REGISTER (PHY CTRL) BITS ------- */
#define LAN91C111_PHY_REG_CTRL_RESET DEF_BIT_15 /* 1 : Initiate PHY reset. */
#define LAN91C111_PHY_REG_CTRL_LPBK_DIS DEF_BIT_NONE /* 0 : PHY Lpbk EN (dflt). */
#define LAN91C111_PHY_REG_CTRL_LPBK_EN DEF_BIT_14 /* 1 : PHY Lpbk DIS. */
#define LAN91C111_PHY_REG_CTRL_SPD_10 DEF_BIT_NONE /* 0 : 10 Mbps. */
#define LAN91C111_PHY_REG_CTRL_SPD_100 DEF_BIT_13 /* 1 : 100 Mbps (dflt). */
#define LAN91C111_PHY_REG_CTRL_NEG_MAN DEF_BIT_NONE /* 0 : Auto Negotiation DIS. */
#define LAN91C111_PHY_REG_CTRL_NEG_AUTO DEF_BIT_12 /* 1 : Auto Negotiation EN (dflt). */
#define LAN91C111_PHY_REG_CTRL_PWR_ON DEF_BIT_NONE /* 0 : PHY ON (dflt). */
#define LAN91C111_PHY_REG_CTRL_PWR_OFF DEF_BIT_11 /* 1 : PHY OFF. */
#define LAN91C111_PHY_REG_CTRL_MII_EN DEF_BIT_NONE /* 0 : Internal PHY EN. */
#define LAN91C111_PHY_REG_CTRL_MII_DIS DEF_BIT_10 /* 1 : Internal PHY DIS/Isolated (dflt). */
#define LAN91C111_PHY_REG_CTRL_NEG_DIS DEF_BIT_NONE /* 0 : Indicates Auto Negotiation DIS (dflt). */
#define LAN91C111_PHY_REG_CTRL_NEG_AUTO_RESET DEF_BIT_09 /* 1 : Initiate Auto Negotiation Reset. */
#define LAN91C111_PHY_REG_CTRL_DPLX_HALF DEF_BIT_NONE /* 0 : Half Dplx (dflt). */
#define LAN91C111_PHY_REG_CTRL_DPLX_FULL DEF_BIT_08 /* 1 : Full Dplx. */
#define LAN91C111_PHY_REG_CTRL_COLL_DIS DEF_BIT_NONE /* 0 : Collision Test DIS (dflt). */
#define LAN91C111_PHY_REG_CTRL_COLL_EN DEF_BIT_07 /* 1 : Collision Test EN. */
/* ---- PHYSICAL STATUS REGISTER (PHY STATUS) BITS ---- */
#define LAN91C111_PHY_REG_STATUS_T4 DEF_BIT_15 /* 1 : 100 Base-T4 PHY. */
#define LAN91C111_PHY_REG_STATUS_TXF DEF_BIT_14 /* 1 : 100 Base-X full dplx PHY. */
#define LAN91C111_PHY_REG_STATUS_TXH DEF_BIT_13 /* 1 : 100 Base-X half dplx PHY. */
#define LAN91C111_PHY_REG_STATUS_TF DEF_BIT_12 /* 1 : 10 Base full dplx PHY. */
#define LAN91C111_PHY_REG_STATUS_TH DEF_BIT_11 /* 1 : 10 Base half dplx PHY. */
#define LAN91C111_PHY_REG_STATUS_RX_PREAMBLE DEF_BIT_NONE /* 0 : Rx Preamble required. */
#define LAN91C111_PHY_REG_STATUS_NO_PREAMBLE DEF_BIT_06 /* 1 : Rx Preamble NOT required. */
#define LAN91C111_PHY_REG_STATUS_NEG_FAIL DEF_BIT_NONE /* 0 : Auto Negotiation NOT complete. */
#define LAN91C111_PHY_REG_STATUS_NEG_ACK DEF_BIT_05 /* 1 : Auto Negotiation complete/ack. */
#define LAN91C111_PHY_REG_STATUS_REM_OK DEF_BIT_NONE /* 0 : NO rem flt. */
#define LAN91C111_PHY_REG_STATUS_REM_FLT DEF_BIT_04 /* 1 : Rem flt. */
#define LAN91C111_PHY_REG_STATUS_NEG_MAN DEF_BIT_NONE /* 0 : Auto Negotiation NOT possible. */
#define LAN91C111_PHY_REG_STATUS_NEG_AUTO DEF_BIT_03 /* 1 : Auto Negotiation possible. */
#define LAN91C111_PHY_REG_STATUS_LINK_FAIL DEF_BIT_NONE /* 0 : Invalid/NO link. */
#define LAN91C111_PHY_REG_STATUS_LINK_OK DEF_BIT_02 /* 1 : Valid link. */
#define LAN91C111_PHY_REG_STATUS_NO_JABBER DEF_BIT_NONE /* 0 : 10 Mbps jabber NOT detected. */
#define LAN91C111_PHY_REG_STATUS_JABBER DEF_BIT_01 /* 1 : 10 Mbps jabber detected. */
#define LAN91C111_PHY_REG_STATUS_REG_NO_EXT DEF_BIT_NONE /* 0 : NO extended regs. */
#define LAN91C111_PHY_REG_STATUS_REG_EXT DEF_BIT_00 /* 1 : Extended regs. */
/*$PAGE*/
/*
*********************************************************************************************************
* LAN91C111 PACKET FRAMES
*
* Note(s) : (1) See SMSC LAN91C111, Section 8.1 for LAN91C111 packet frame summary :
*
* Packet
* Offset
* --- |-----------------------------------|
* ^ 0 | STATUS WORD |
* | |-----------------------------------|
* | 2 | RESERVED | PACKET SIZE |
* | |-----------------------------------|
* | 4 | |
* | |
* 2048 | |
* octets / /
* maximum PACKET DATA
* / /
* | | |
* | | |
* | | |
* | |-----------------------------------|
* v | CONTROL | LAST DATA OCTET |
* --- |-----------------------------------|
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