📄 net_nic.c
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* (a) For single-register, single-access; critical sections are implemented in LAN91C111_RegRd()
* & LAN91C111_RegWr().
*
* (b) For read-modify-write register access OR multiple-register-access sequences; critical
* sections &/or mutual exclusion enclosing the entire register access/sequence is REQUIRED.
*********************************************************************************************************
*/
/*$PAGE*/
/* ------------------- REG BANKS ------------------ */
#define LAN91C111_REG_BANK_0 0x0000
#define LAN91C111_REG_BANK_1 0x0001
#define LAN91C111_REG_BANK_2 0x0002
#define LAN91C111_REG_BANK_3 0x0003
#define LAN91C111_REG_BANK_DFLT LAN91C111_REG_BANK_0
/* --------------------- REGS --------------------- */
#define LAN91C111_REG_BANK_SEL_OFFSET 0x000E
/* ------------------ BANK 0 REGS ----------------- */
#define LAN91C111_REG_TCR_BANK LAN91C111_REG_BANK_0
#define LAN91C111_REG_TCR_OFFSET 0x0000
#define LAN91C111_REG_EPH_BANK LAN91C111_REG_BANK_0
#define LAN91C111_REG_EPH_OFFSET 0x0002
#define LAN91C111_REG_RCR_BANK LAN91C111_REG_BANK_0
#define LAN91C111_REG_RCR_OFFSET 0x0004
#define LAN91C111_REG_CTR_BANK LAN91C111_REG_BANK_0
#define LAN91C111_REG_CTR_OFFSET 0x0006
#define LAN91C111_REG_MIR_BANK LAN91C111_REG_BANK_0
#define LAN91C111_REG_MIR_OFFSET 0x0008
#define LAN91C111_REG_RPCR_BANK LAN91C111_REG_BANK_0
#define LAN91C111_REG_RPCR_OFFSET 0x000A
#define LAN91C111_REG_RESERVED_0_BANK LAN91C111_REG_BANK_0
#define LAN91C111_REG_RESERVED_0_OFFSET 0x000C
#define LAN91C111_REG_BANK_SEL_0_BANK LAN91C111_REG_BANK_0
#define LAN91C111_REG_BANK_SEL_0_OFFSET LAN91C111_REG_BANK_SEL_OFFSET
/* ------------------ BANK 1 REGS ----------------- */
#define LAN91C111_REG_CFG_BANK LAN91C111_REG_BANK_1
#define LAN91C111_REG_CFG_OFFSET 0x0000
#define LAN91C111_REG_BASE_BANK LAN91C111_REG_BANK_1
#define LAN91C111_REG_BASE_OFFSET 0x0002
#define LAN91C111_REG_MAC_0_BANK LAN91C111_REG_BANK_1
#define LAN91C111_REG_MAC_0_OFFSET 0x0004
#define LAN91C111_REG_MAC_2_BANK LAN91C111_REG_BANK_1
#define LAN91C111_REG_MAC_2_OFFSET 0x0006
#define LAN91C111_REG_MAC_4_BANK LAN91C111_REG_BANK_1
#define LAN91C111_REG_MAC_4_OFFSET 0x0008
#define LAN91C111_REG_GENERAL_BANK LAN91C111_REG_BANK_1
#define LAN91C111_REG_GENERAL_OFFSET 0x000A
#define LAN91C111_REG_CTRL_BANK LAN91C111_REG_BANK_1
#define LAN91C111_REG_CTRL_OFFSET 0x000C
#define LAN91C111_REG_BANK_SEL_1_BANK LAN91C111_REG_BANK_1
#define LAN91C111_REG_BANK_SEL_1_OFFSET LAN91C111_REG_BANK_SEL_OFFSET
/* ------------------ BANK 2 REGS ----------------- */
#define LAN91C111_REG_MMU_BANK LAN91C111_REG_BANK_2
#define LAN91C111_REG_MMU_OFFSET 0x0000
#define LAN91C111_REG_PNR_BANK LAN91C111_REG_BANK_2
#define LAN91C111_REG_PNR_OFFSET 0x0002
#define LAN91C111_REG_FIFO_BANK LAN91C111_REG_BANK_2
#define LAN91C111_REG_FIFO_OFFSET 0x0004
#define LAN91C111_REG_PTR_BANK LAN91C111_REG_BANK_2
#define LAN91C111_REG_PTR_OFFSET 0x0006
#define LAN91C111_REG_DATA_0_BANK LAN91C111_REG_BANK_2
#define LAN91C111_REG_DATA_0_OFFSET 0x0008
#define LAN91C111_REG_DATA_2_BANK LAN91C111_REG_BANK_2
#define LAN91C111_REG_DATA_2_OFFSET 0x000A
#define LAN91C111_REG_INT_BANK LAN91C111_REG_BANK_2
#define LAN91C111_REG_INT_OFFSET 0x000C
#define LAN91C111_REG_BANK_SEL_2_BANK LAN91C111_REG_BANK_2
#define LAN91C111_REG_BANK_SEL_2_OFFSET LAN91C111_REG_BANK_SEL_OFFSET
/* ------------------ BANK 3 REGS ----------------- */
#define LAN91C111_REG_MULTICAST_0_BANK LAN91C111_REG_BANK_3
#define LAN91C111_REG_MULTICAST_0_OFFSET 0x0000
#define LAN91C111_REG_MULTICAST_2_BANK LAN91C111_REG_BANK_3
#define LAN91C111_REG_MULTICAST_2_OFFSET 0x0002
#define LAN91C111_REG_MULTICAST_4_BANK LAN91C111_REG_BANK_3
#define LAN91C111_REG_MULTICAST_4_OFFSET 0x0004
#define LAN91C111_REG_MULTICAST_6_BANK LAN91C111_REG_BANK_3
#define LAN91C111_REG_MULTICAST_6_OFFSET 0x0006
#define LAN91C111_REG_MGMT_BANK LAN91C111_REG_BANK_3
#define LAN91C111_REG_MGMT_OFFSET 0x0008
#define LAN91C111_REG_REV_BANK LAN91C111_REG_BANK_3
#define LAN91C111_REG_REV_OFFSET 0x000A
#define LAN91C111_REG_ERCV_BANK LAN91C111_REG_BANK_3
#define LAN91C111_REG_ERCV_OFFSET 0x000C
#define LAN91C111_REG_BANK_SEL_3_BANK LAN91C111_REG_BANK_3
#define LAN91C111_REG_BANK_SEL_3_OFFSET LAN91C111_REG_BANK_SEL_OFFSET
/*$PAGE*/
/*
*********************************************************************************************************
* LAN91C111 REGISTER BITS
*********************************************************************************************************
*/
/* ------- TRANSMIT CONTROL REGISTER (TCR) BITS ------- */
#define LAN91C111_REG_TCR_SW_DPLX_HALF DEF_BIT_NONE /* 0 : Half Dplx (dflt). */
#define LAN91C111_REG_TCR_SW_DPLX_FULL DEF_BIT_15 /* 1 : Full Dplx. */
#define LAN91C111_REG_TCR_EPH_LPBK_DIS DEF_BIT_NONE /* 0 : EPH Lpbk DIS (dflt). */
#define LAN91C111_REG_TCR_EPH_LPBK_EN DEF_BIT_13 /* 1 : EPH Lpbk EN. */
#define LAN91C111_REG_TCR_SQET_STOP_DIS DEF_BIT_NONE /* 0 : Ignores SQET (dflt). */
#define LAN91C111_REG_TCR_SQET_STOP_EN DEF_BIT_12 /* 1 : Traps SQET. */
#define LAN91C111_REG_TCR_RX_LPBK_DIS DEF_BIT_NONE /* 0 : Rx Lpbk DIS (dflt). */
#define LAN91C111_REG_TCR_RX_LPBK_EN DEF_BIT_11 /* 1 : Rx Lpbk EN. */
#define LAN91C111_REG_TCR_MON_CARR_DIS DEF_BIT_NONE /* 0 : Ignore Carrier (dflt). */
#define LAN91C111_REG_TCR_MON_CARR_EN DEF_BIT_10 /* 1 : Monitor Carrier. */
#define LAN91C111_REG_TCR_TX_CRC_EN DEF_BIT_NONE /* 0 : Tx CRC appended (dflt). */
#define LAN91C111_REG_TCR_TX_CRC_DIS DEF_BIT_08 /* 1 : Tx CRC NOT appended. */
#define LAN91C111_REG_TCR_TX_PAD_DIS DEF_BIT_NONE /* 0 : Tx frames NOT padded (dflt). */
#define LAN91C111_REG_TCR_TX_PAD_EN DEF_BIT_07 /* 1 : Tx frames padded. */
#define LAN91C111_REG_TCR_TX_COLL_NOT_FORCED DEF_BIT_NONE /* 0 : Tx Collisions NOT forced (dflt). */
#define LAN91C111_REG_TCR_TX_COLL_FORCED DEF_BIT_02 /* 1 : Tx Collisions forced. */
#define LAN91C111_REG_TCR_LPBK_OUT_LO DEF_BIT_NONE /* 0 : Force Lpbk output pin LO (dflt). */
#define LAN91C111_REG_TCR_LPBK_OUT_HI DEF_BIT_01 /* 1 : Force Lpbk output pin HI. */
#define LAN91C111_REG_TCR_TX_DIS DEF_BIT_NONE /* 0 : Tx DIS (dflt). */
#define LAN91C111_REG_TCR_TX_EN DEF_BIT_00 /* 1 : Tx EN. */
/* ------- RECEIVE CONTROL REGISTER (RCR) BITS -------- */
#define LAN91C111_REG_RCR_SW_RESET DEF_BIT_15 /* 1 : Initiate SW reset. */
#define LAN91C111_REG_RCR_RX_FLTR_CARR_DIS DEF_BIT_NONE /* 0 : Rx frames immediately (dflt). */
#define LAN91C111_REG_RCR_RX_FLTR_CARR_EN DEF_BIT_14 /* 1 : Rx frames after 12-bit carrier sense. */
#define LAN91C111_REG_RCR_RX_COLL_EN DEF_BIT_NONE /* 0 : Do NOT abort Rx Collision frames (dflt). */
#define LAN91C111_REG_RCR_RX_COLL_DIS DEF_BIT_13 /* 1 : Abort Rx Collision frames. */
#define LAN91C111_REG_RCR_RX_CRC_EN DEF_BIT_NONE /* 0 : Rx CRC appended (dflt). */
#define LAN91C111_REG_RCR_RX_CRC_DIS DEF_BIT_09 /* 1 : Rc CRC NOT appended. */
#define LAN91C111_REG_RCR_RX_DIS DEF_BIT_NONE /* 0 : Rx DIS (dflt). */
#define LAN91C111_REG_RCR_RX_EN DEF_BIT_08 /* 1 : Rx EN. */
#define LAN91C111_REG_RCR_RX_MULTICAST_TBL DEF_BIT_NONE /* 0 : Rx Tbl Multicast addrs ONLY (dflt). */
#define LAN91C111_REG_RCR_RX_MULTICAST_ALL DEF_BIT_02 /* 1 : Rx ALL Multicast addrs. */
#define LAN91C111_REG_RCR_RX_PROMISC_DIS DEF_BIT_NONE /* 0 : Rx dest frames ONLY (dflt). */
#define LAN91C111_REG_RCR_RX_PROMISC_EN DEF_BIT_01 /* 1 : Rx ALL frames. */
/* --- RECEIVE/PHYSICAL CONTROL REGISTER (RPCR) BITS --- */
#define LAN91C111_REG_RPCR_SPD_10 DEF_BIT_NONE /* 0 : 10 Mbps (dlft). */
#define LAN91C111_REG_RPCR_SPD_100 DEF_BIT_13 /* 1 : 100 Mbps. */
#define LAN91C111_REG_RPCR_DPLX_HALF DEF_BIT_NONE /* 0 : Half Dplx (dflt). */
#define LAN91C111_REG_RPCR_DPLX_FULL DEF_BIT_12 /* 1 : Full Dplx. */
#define LAN91C111_REG_RPCR_AUTO_NEG_DIS DEF_BIT_NONE /* 0 : Auto Negotiation DIS (dflt). */
#define LAN91C111_REG_RPCR_AUTO_NEG_EN DEF_BIT_11 /* 1 : Auto Negotiation EN. */
/* LED SELECT SIGNAL - LED A */
#define LAN91C111_REG_RPCR_LED_A_LINK 0x0000 /* 0 : Logical OR of 100 Mbps or 10 Mbps link detected */
#define LAN91C111_REG_RPCR_LED_A_LINK_10 0x0040 /* 2 : 10 Mbps link detected */
#define LAN91C111_REG_RPCR_LED_A_FULL_DUPLEX 0x0060 /* 3 : Full Duplex Mode Enabled */
#define LAN91C111_REG_RPCR_LED_A_RX_TX 0x0080 /* 4 : Tx or Rx packet occurred */
#define LAN91C111_REG_RPCR_LED_A_LINK_100 0x00A0 /* 5 : 100 Mbps link detected */
#define LAN91C111_REG_RPCR_LED_A_RX 0x00C0 /* 6 : Rx packet occurred */
#define LAN91C111_REG_RPCR_LED_A_TX 0x00E0 /* 7 : Tx packet occurred */
/* LED SELECT SIGNAL - LED B */
#define LAN91C111_REG_RPCR_LED_B_LINK 0x0000 /* 0 : Logical OR of 100 Mbps or 10 Mbps link detected */
#define LAN91C111_REG_RPCR_LED_B_LINK_10 0x0008 /* 2 : 10 Mbps link detected */
#define LAN91C111_REG_RPCR_LED_B_FULL_DUPLEX 0x000C /* 3 : Full Duplex Mode Enabled */
#define LAN91C111_REG_RPCR_LED_B_RX_TX 0x0010 /* 4 : Tx or Rx packet occurred */
#define LAN91C111_REG_RPCR_LED_B_LINK_100 0x0014 /* 5 : 100 Mbps link detected */
#define LAN91C111_REG_RPCR_LED_B_RX 0x0018 /* 6 : Rx packet occurred */
#define LAN91C111_REG_RPCR_LED_B_TX 0x001C /* 7 : Tx packet occurred */
/* -------- CONFIGURATION REGISTER (CFG) BITS --------- */
#define LAN91C111_REG_CFG_EPH_LO_PWR_EN DEF_BIT_NONE /* 0 : EPH Lo Pwr Mode EN (dflt). */
#define LAN91C111_REG_CFG_EPH_LO_PWR_DIS DEF_BIT_15 /* 1 : EPH Lo Pwr Mode DIS. */
#define LAN91C111_REG_CFG_WAIT_STATES_EN DEF_BIT_NONE /* 0 : Wait states EN (dflt). */
#define LAN91C111_REG_CFG_WAIT_STATES_DIS DEF_BIT_12 /* 1 : Wait states DIS. */
#define LAN91C111_REG_CFG_PHY_INT DEF_BIT_NONE /* 0 : Internal PHY (dlft). */
#define LAN91C111_REG_CFG_PHY_EXT DEF_BIT_09 /* 1 : External PHY. */
/* ----------- CONTROL REGISTER (CTRL) BITS ----------- */
#define LAN91C111_REG_CTRL_RX_CRC_ERR_DIS DEF_BIT_NONE /* 0 : Abort Rx CRC err frames (dflt). */
#define LAN91C111_REG_CTRL_RX_CRC_ERR_EN DEF_BIT_14 /* 1 : Do NOT abort Rx CRC err frames. */
#define LAN91C111_REG_CTRL_TX_REL_MAN DEF_BIT_NONE /* 0 : Manual rel Tx pkts (dflt). */
#define LAN91C111_REG_CTRL_TX_REL_AUTO DEF_BIT_11 /* 1 : Auto rel Tx pkts. */
#define LAN91C111_REG_CTRL_LINK_ERR_DIS DEF_BIT_NONE /* 0 : Link Err Int DIS (dflt). */
#define LAN91C111_REG_CTRL_LINK_ERR_EN DEF_BIT_07 /* 1 : Link Err Int EN. */
#define LAN91C111_REG_CTRL_CTR_ERR_DIS DEF_BIT_NONE /* 0 : Ctr Ovf Int DIS (dflt). */
#define LAN91C111_REG_CTRL_CTR_ERR_EN DEF_BIT_06 /* 1 : Ctr Ovf Int EN. */
#define LAN91C111_REG_CTRL_TX_ERR_DIS DEF_BIT_NONE /* 0 : Tx Err Int DIS (dflt). */
#define LAN91C111_REG_CTRL_TX_ERR_EN DEF_BIT_05 /* 1 : Tx Err Int EN. */
#define LAN91C111_REG_CTRL_EEPROM_DFLT DEF_BIT_NONE /* 0 : CFG/BASE/MAC Regs (dflt). */
#define LAN91C111_REG_CTRL_EEPROM_GENERAL DEF_BIT_02 /* 1 : GEN Reg ONLY. */
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