📄 net_nic.c
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/*
*********************************************************************************************************
* uC/TCP-IP
* The Embedded TCP/IP Suite
*
* (c) Copyright 2003-2006; Micrium, Inc.; Weston, FL
*
* All rights reserved. Protected by international copyright laws.
*
* uC/TCP-IP is provided in source form for FREE evaluation, for educational
* use or peaceful research. If you plan on using uC/TCP-IP in a commercial
* product you need to contact Micrium to properly license its use in your
* product. We provide ALL the source code for your convenience and to help
* you experience uC/TCP-IP. The fact that the source code is provided does
* NOT mean that you can use it without paying a licensing fee.
*
* Network Interface Card (NIC) port files provided, as is, for FREE and do
* NOT require any additional licensing or licensing fee.
*
* Knowledge of the source code may NOT be used to develop a similar product.
*
* Please help us continue to provide the Embedded community with the finest
* software available. Your honesty is greatly appreciated.
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
* NETWORK INTERFACE CARD
*
* LAN91C111
*
* Filename : net_nic.c
* Version : V1.87
* Programmer(s) : ITJ
* JJL
*********************************************************************************************************
* Note(s) : (1) Supports LAN91C111 Ethernet controller as described in
*
* Standard Microsystems Corporation's (SMSC; http://www.smsc.com)
* (a) LAN91C111 data sheet (SMSC LAN91C111; Revision B 09/17/2002)
* (b) LAN91C111 Application Note 9.6 (SMSC AN9.6; Revision 11/25/2002)
*
* (2) REQUIREs Ethernet Network Interface Layer located in the following network directory :
*
* \<Network Protocol Suite>\IF\Ether\
*
* where
* <Network Protocol Suite> directory path for network protocol suite
*
* (3) LAN91C111 is implemented with a Little-endian architecture.
*
* (a) This driver accesses ALL registers & data as 16-bit Little-endian words.
* I.e. lower-octets start on an even-valued address/offset while upper-octets
* immediately follow on an odd -valued address/offset equal to the lower-
* octet address/offset plus one (1).
*
* (b) This driver requires that ONLY the 16 least significant data lines (D15 - D00)
* are used & that the LAN91C111's Byte Enable lines (BE3 - BE0) are configured to
* access 16-bit words (see SMSC AN9.6, Section 3.5.10) :
*
* BE0 = BE1 = Active-Low 0 Lower-16 bits ENABLED
* BE1 = BE2 = Active-Low 1 Upper-16 bits DISABLED
*
* (c) Since this driver implements Little-endian word access (see Note #3a), LAN91C111
* register access does NOT require octet-swapping.
*
* Therefore, for connection to any processor, Big-endian or Little-endian, the
* LAN91C111's 16 least significant data lines should be directly connected to the
* processor's 16 least significant data lines :
*
* ------------- -------------
* | LAN91C111 | | CPU |
* | | | |
* | | | |
* | D07- | 8 | D07- |
* | D00 |--------/--------| D00 |
* | | | |
* | D15- | 8 | D15- |
* | D08 |--------/--------| D08 |
* | | | |
* ------------- -------------
*
* Product-specific I/O functions NetNIC_Rd_16() & NetNIC_Wr_16() MUST NOT swap
* the upper- & lower-octets for 16-bit word accesses.
*
*
* If the connection to any processor, Big-endian or Little-endian, octet-swaps
* the LAN91C111's 16 least significant data lines with the processor's 16 least
* significant data lines :
*
* ------------- -------------
* | LAN91C111 | | CPU |
* | | | |
* | | | |
* | D07- | 8 | D15- |
* | D00 |--------/--------| D08 |
* | | | |
* | D15- | 8 | D07- |
* | D08 |--------/--------| D00 |
* | | | |
* ------------- -------------
*
* then product-specific I/O functions NetNIC_Rd_16() & NetNIC_Wr_16() MUST re-swap
* the upper- & lower-octets for 16-bit word accesses using LAN91C111_NIC_TO_HOST_16()
* & LAN91C111_HOST_TO_NIC_16() macro's, respectively.
*
*$PAGE
* (d) Since this driver implements Little-endian word access (see Note #3a), LAN91C111
* data access to & from packet frames MUST be octet-swapped for connections to a
* Big-endian processor. However, the driver performs this octet-swap internally
* through use of LAN91C111_NIC_TO_HOST_16() & LAN91C111_HOST_TO_NIC_16() macro's
* (see 'LAN91C111 WORD ORDER - TO - CPU WORD ORDER').
*
* (4) #### Link detection & recovery state machine NOT yet implemented.
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* INCLUDE FILES
*********************************************************************************************************
*/
#define NET_NIC_MODULE
#include <net.h>
/*
*********************************************************************************************************
* LOCAL DEFINES
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* LAN91C111 DEFINES
*********************************************************************************************************
*/
#define LAN91C111_INIT_AUTO_NEG_RETRIES 5
#define LAN91C111_TX_ALLOC_INIT_RETRIES 5
/*
*********************************************************************************************************
* LAN91C111 WORD ORDER - TO - CPU WORD ORDER
*
* Note(s) : (1) Since LAN91C111 is implemented with a Little-endian architecture (see this 'net_nic.h
* Note #3'), & this driver accesses ALL words as 16-bit Little-endian (see this 'net_nic.h
* Note #3a'), then data access MUST be octet-swapped for Big-engian processors & MUST NOT
* be swapped for Little-endian processors (see this 'net_nic.h Note #3d').
*********************************************************************************************************
*/
#if (CPU_CFG_ENDIAN_TYPE == CPU_ENDIAN_TYPE_BIG)
#define LAN91C111_NIC_TO_HOST_16(val) ((((CPU_INT16U)(val) & 0xFF00) >> 8) | \
(((CPU_INT16U)(val) & 0x00FF) << 8))
#else
#define LAN91C111_NIC_TO_HOST_16(val) (val)
#endif
#define LAN91C111_HOST_TO_NIC_16(val) LAN91C111_NIC_TO_HOST_16(val)
/*$PAGE*/
/*
*********************************************************************************************************
* LAN91C111 REGISTERS
*
* Note(s) : (1) See SMSC LAN91C111, Sections 8.3 - 8.26 for LAN91C111 register summary.
*
* (2) LAN91C111 registers accessed & modified by appropriately configuring the LAN91C111 Bank
* Select Register & by addressing the desired register address offset(s).
*
* (a) A register can ONLY be accessed when that register's bank select value is configured/
* written into the Bank Select Register (see SMSC LAN91C111, Section 8.4) :
*
* 1 1 1 1 1 1
* 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* ---------------------------------
* |x x x x x x x x x x x x x| BNK |
* ---------------------------------
* LAN91C111 Bank Select Register
*
* where
*
* BNK Indicates register's bank :
* '000' - Bank 0
* '001' - Bank 1
* '010' - Bank 2
* '011' - Bank 3
*
* (b) After the Bank Select Register is configured with the appropriate register bank value,
* a register is accessed by addressing the appropriate offset from the base register address
* (see SMSC LAN91C111, Section 8.3) :
*
* 1 1 1 1 1 1
* 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* ---------------------------------
* |x x x x x x x x x x x x|OFFSET |
* ---------------------------------
* Register Address Offset
*
* where
*
* OFFSET Indicates register's offset from the base register address :
* '0000' - lowest register offset
* '1110' - highest 16-bit register offset
* '1100' - highest 32-bit register offset
*
* Mapping of register bank & offset values to physical registers is implemented by LAN91C111_RegRd()
* & LAN91C111_RegWr() that call product-specific I/O functions NetNIC_Rd_16() & NetNIC_Wr_16(). These
* functions perform the actual read & write to the LAN91C111 & MUST be developer-implemented in
*
* \<Your Product Application>\net_bsp.c
*
* where
* <Your Product Application> directory path for Your Product's Application
*
* (3) The current register bank select is maintained using a virtual copy of the LAN91C111's current
* Bank Select Register value. Each time a register is accessed, its register bank is compared
* to the maintained, virtual copy of the current register bank. If the banks are the same, then
* the register's bank is already configured as the current bank in the Bank Select Register & no
* bank select configuration is required. If the banks are different, then the register's bank
* value MUST be configured into the Bank Select Register (see Note #2a). This reduces the total
* number of Bank Select Register writes required.
*
* (4) Registers referenced as offsets from a base register address (see Note #2b). The base register
* address MUST be correctly implemented in product-specific I/O functions NetNIC_Rd_16() &
* NetNIC_Wr_16(). See SMSC LAN91C111, Section 5 'Address' & Section 8.3; & SMSC AN9.6 3.3 for
* LAN91C111 Base Register address summary.
*
* (5) To protect LAN91C111 register accesses during multi-thread operation, registers MUST be
* accessed in critical sections &/or mutual exclusion.
*
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