📄 mass_stg.lst
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599 {
600 1 while(USB0ADR>>7);
601 1 USB0ADR = addr;
602 1 USB0DAT = dat;
603 1
604 1 }
605
606 /********************************************************************************************
607 name: SFR_RD
608 function: read the content of the address in USB0ADR
609 pars: addr
610 returns: dat
611 *********************************************************************************************/
612 uchar SFR_RD(uchar addr)
613 {
614 1 uchar dat;
615 1 while(USB0ADR>>7);
616 1 USB0ADR = 0x80 + addr;
617 1 while(USB0ADR>>7);
618 1 dat = USB0DAT;
619 1 return dat;
620 1
621 1 }
622
623 /**********************************************************************************************
624 name: Swap
625 function: Swap the 8bit High and 8bit Low
626 pars: dat
627 renturns: Swap_dat
628 ***********************************************************************************************/
629 uint Swap(uint dat)
630 {
631 1 uint Swap_dat;
632 1 Swap_dat = dat>>8 | dat<<8;
633 1 return Swap_dat;
634 1
635 1 }
636
637 /**********************************************************************************************
638 name: FIFO_WR
639 function: write data to the output fifo
640 pars: ptr(data pointer), addr(fifo address), num(length)
641 returns: no
642 ***********************************************************************************************/
643 void FIFO_WR(uchar *ptr, uchar addr, uint num) reentrant
644 {
645 1 uint i;
646 1 USB0ADR = addr;
647 1 for(i=0;i<num;i++)
648 1 {
649 2 while(USB0ADR>>7);
650 2 USB0DAT = *(ptr + i);
651 2 }
652 1
653 1 }
654
C51 COMPILER V7.06 MASS_STG 10/19/2007 15:26:26 PAGE 12
655
656 /*void FIFO_RD(uchar addr, uchar num)
657 {
658 uchar i;
659 while(USB0ADR>>7);
660 USB0ADR = addr + 0xC0;
661 for(i=0;i<num;i++)
662 {
663 while(USB0ADR>>7);
664 buf[i] = USB0DAT;
665 }
666 }*/
667 /**********************************************************************************************
668 name: Analysis_Requst
669 function: analysis the requst report and ackownlage the host
670 pars: Requst pointer pReq
671 returns: no
672 Note: DATAEND is Stage shakehand signal, INPRDY and OPRDY are Phase shakehand signal
673 EndPoint 0 Control Registor
674 ----------------------------------------------------------------------
675 | SSUEND | SOPRDY | SDSTL| SUEND | DATAEND | STSTL | INPRDY | OPRDY |
676 | | | | | | | | |
677 ----------------------------------------------------------------------
678 ***********************************************************************************************/
679 void Analysis_Requst(Requst * ptr)
680 {
681 1 uchar type, index; //Variables must be defined in front of
682 1 uint requst;
683 1 uint value;
684 1 uint num; //the Code Area
685 1
686 1
687 1 Config_Descriptor * pConfig;
688 1 Interface_Descriptor * pInterface;
689 1 Config_Long * pConfig_Long;
690 1 Device_Descriptor * pDevice; //fore Convert the Structure Type to
691 1 pDevice = & device_descriptor; //unsigned character
692 1 pConfig = & config_descriptor;
693 1 pInterface = & interface_descriptor;
694 1 pConfig_Long = & config_long;
695 1
696 1
697 1 value = ptr->wValue;
698 1 requst = ptr->bRequst;
699 1 num = Swap(ptr->wLength);
700 1 type = (uchar)(ptr->wValue & 0x00FF);
701 1 index = (uchar)((ptr->wValue & 0xFF00)>>8);
702 1
703 1
704 1 switch (requst)
705 1 {
706 2 case Set_Addr:
707 2 {
708 3
709 3 //SFR_WR(FADDR, index);
710 3 //Must not Read Address first, should always return ZERO Length Packet First, then save the Address
711 3 //Otherwise the FADDR is always the Default Address 0x0, the Assigned Address is Random Between 0~127
712 3
713 3 SFR_WR(E0CSR, 0x0A); //Send ACK and indicate DATA END
714 3 SFR_WR(FADDR, index);
715 3 while(SFR_RD(FADDR) & BIT7);
716 3 break;
C51 COMPILER V7.06 MASS_STG 10/19/2007 15:26:26 PAGE 13
717 3
718 3 }
719 2 case Get_Descriptor:
720 2
721 2 switch (type)
722 2 {
723 3
724 3 case DEVICE:
725 3
726 3 FIFO_WR((uchar *)pDevice, FIFO0, num);
727 3 SFR_WR(E0CSR, 0x0A);
728 3
729 3 break;
730 3
731 3 case CONFIG:
732 3 if(num<65) //Requst Config Descriptor Only
733 3 {
734 4 FIFO_WR((uchar *)pConfig, FIFO0, num);
735 4 SFR_WR(E0CSR, 0x0A);
736 4 }
737 3 else
738 3 {
739 4 FIFO_WR((uchar *)pConfig_Long, FIFO0, 0x20); //Requst Full Configuration
740 4 SFR_WR(E0CSR, 0x0A);
741 4
742 4
743 4 }
744 3 break;
745 3
746 3 case STRING:
747 3
748 3
749 3 break;
750 3
751 3 case INTERFACE:
752 3
753 3
754 3 break;
755 3
756 3 case ENDPOINT:
757 3
758 3
759 3
760 3 break;
761 3
762 3
763 3 }
764 2
765 2
766 2 case Set_Config:
767 2
768 2
769 2 break;
770 2
771 2 case Set_Interface:
772 2
773 2
774 2 break;
775 2
776 2 case Get_Max_Lun: //Get the max Logic Unit Number of Device
777 2
778 2 SFR_WR(FIFO0, 0x0);
C51 COMPILER V7.06 MASS_STG 10/19/2007 15:26:26 PAGE 14
779 2 SFR_WR(E0CSR, 0x0A);
780 2 break;
781 2
782 2 case Mass_Storage_Reset: //Reset the Device
783 2
784 2 USB_Config();
785 2 break;
786 2
787 2 }
788 1
789 1
790 1 }
791
792 /***************************************************************************************
793 name: CLR_Flags
794 function: clear the bulk endpoint interrupt flags
795 pars: no
796 returns: no
797 ****************************************************************************************/
798 void CLR_Flags(void)
799 {
800 1 flags.epin1 = 0;
801 1 flags.epout1 = 0;
802 1 }
803
804 /****************************************************************************************
805 name: Analysis_UFI
806 function: analysis the SCSI-UFI commands
807 pars: no
808 returns: no
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