sense.inc

cypress的触摸按键模块介绍calibrating_capsense_with_the_csr_user_module___an2355_13.

;;*****************************************************************************
;;*****************************************************************************
;;  FILENAME:   SENSE.inc
;;   Version: 1.1, Updated on 2005/10/13 at 09:13:22
;;  Generated by PSoC Designer ver 4.2  b1013 : 02 September, 2004
;;
;;  DESCRIPTION:
;;    Assembler declarations for the CSR user module interface
;;    for the 21xxx PSoC family of devices.
;;-----------------------------------------------------------------------------
;;  Copyright (c) Cypress MicroSystems 2000-2005. All Rights Reserved.
;;*****************************************************************************
;;*****************************************************************************


SENSE_CTR_START_BIT:                   equ 0x01   ; CTR Control register start bit
SENSE_PWM_START_BIT:                   equ 0x01   ; PWM Control register start bit
SENSE_CMP_START_BIT:                   equ 0x01   ; CMP CR2 register start bit
SENSE_SCAN_INT_REG:                    equ 0x0e1
SENSE_SCAN_INT_MASK:                   equ 0x01

SENSE_Method:                          equ 1
SENSE_Method_Freq:                     equ 0
SENSE_Method_Period:                   equ 1

;--------------------------------------------------
; Constants for SENSE API's
;--------------------------------------------------
SENSE_SCAN_CONTINUOUS:                 equ 0x01
SENSE_SCAN_ONCE:                       equ 0x00

SENSE_SCAN_ACTIVE:                     equ 0x10   ; Set when scanning is active
SENSE_SCAN_SET_COMPLETE:               equ 0x20   ; Set each time a set of keys is scanned.

SENSE_ButtonCount:                     equ 0x8
SENSE_SliderCount:                     equ 0x0
SENSE_TotalSwitchCount:                equ 0x8

SENSE_DAC_LOW:                         equ 0x00
SENSE_DAC_HIGH:                        equ 0x01

SENSE_ESD_DETECTION:                   equ 0x8
SENSE_BUTTONS_EXIST:                   equ 0x8
SENSE_SLIDERS_EXIST:                   equ 0x0

;--------------------------------------------------
; Registers Address Constants for SENSE
;--------------------------------------------------

SENSE_PWM_FUNC_REG:                    equ 0x20             ; PWM Function Reg
SENSE_PWM_IN_REG:                      equ 0x21             ; PWM Input Reg 
SENSE_PWM_OUT_REG:                     equ 0x22             ; PWM Output Reg       
SENSE_PWM_COUNTER_REG:                 equ 0x20             ; PWM Counter Reg       
SENSE_PWM_PERIOD_REG:                  equ 0x21             ; PWM Period Reg       
SENSE_PWM_COMPARE_REG:                 equ 0x22             ; PWM Compare Reg       
SENSE_PWM_CONTROL_REG:                 equ 0x23             ; PWM Control Reg       

SENSE_ACE_CONTROL1_REG:                equ 0x72             ; PWM Function Register
SENSE_ACE_CONTROL2_REG:                equ 0x73             ; PWM Function Register

SENSE_CTR_COUNTER_LSB_REG:             equ 0x24             ; CTR LSB Counter Reg  
SENSE_CTR_PERIOD_LSB_REG:              equ 0x25             ; CTR LSB Period Reg
SENSE_CTR_COMPARE_LSB_REG:             equ 0x26             ; CTR LSB Compare Reg
SENSE_CTR_CONTROL_LSB_REG:             equ 0x27             ; CTR LSB Control Reg
SENSE_CTR_FUNC_LSB_REG:                equ 0x24             ; CTR LSB Function Reg
SENSE_CTR_INPUT_LSB_REG:               equ 0x25             ; CTR LSB Input Reg
SENSE_CTR_OUTPUT_LSB_REG:              equ 0x26             ; CTR LSB Output Reg

SENSE_CTR_COUNTER_MSB_REG:             equ 0x28             ; CTR MSB Counter Reg  
SENSE_CTR_PERIOD_MSB_REG:              equ 0x29             ; CTR MSB Period Reg
SENSE_CTR_COMPARE_MSB_REG:             equ 0x2a             ; CTR MSB Compare Reg
SENSE_CTR_CONTROL_MSB_REG:             equ 0x2b             ; CTR MSB Control Reg
SENSE_CTR_FUNC_MSB_REG:                equ 0x28             ; CTR MSB Function Reg
SENSE_CTR_INPUT_MSB_REG:               equ 0x29             ; CTR MSB Input Reg
SENSE_CTR_OUTPUT_MSB_REG:              equ 0x2a             ; CTR MSB Output Reg


DR_OFFSET:                             equ 0x00
DM0_OFFSET:                            equ 0x00             ; Bank 1
DM1_OFFSET:                            equ 0x01             ; Bank 1
DM2_OFFSET:                            equ 0x03             ; Bank 0
MUX_OFFSET:                            equ MUX_CR0          ; Bank 1

;--------------------------------------------------
; SENSE Macro 'Functions'
;--------------------------------------------------

   macro SENSE_Start_M
   or    reg[SENSE_CTR_CONTROL_LSB_REG],  SENSE_CTR_START_BIT
   or    reg[SENSE_PWM_CONTROL_REG],      SENSE_PWM_START_BIT
   endm

   macro SENSE_Start_Counter_M
   or    reg[SENSE_CTR_CONTROL_LSB_REG],  SENSE_CTR_START_BIT
   endm

   macro SENSE_Start_CMP_M
   mov   reg[SENSE_ACE_CONTROL2_REG],     SENSE_CMP_START_BIT
   endm

   macro SENSE_Stop_M
   and   reg[SENSE_PWM_CONTROL_REG],     ~SENSE_PWM_START_BIT
   and   reg[SENSE_CTR_CONTROL_LSB_REG], ~SENSE_CTR_START_BIT
   endm

   macro SENSE_Stop_Counter_M
   and   reg[SENSE_CTR_CONTROL_LSB_REG], ~SENSE_CTR_START_BIT
   endm

   macro SENSE_Stop_CMP_M
   mov   reg[SENSE_ACE_CONTROL2_REG],    ~SENSE_CMP_START_BIT
   endm

   macro SENSE_EnableInt_M
   M8C_EnableIntMask SENSE_SCAN_INT_REG, SENSE_SCAN_INT_MASK
   endm

   macro SENSE_DisableInt_M
   M8C_DisableIntMask SENSE_SCAN_INT_REG, SENSE_SCAN_INT_MASK
   endm      

; end of file SENSE.inc