psocgpioint.h

cypress的触摸按键模块介绍calibrating_capsense_with_the_csr_user_module___an2355_13.

#pragma	ioport	INT_IntEn_ADDR:	0x5
BYTE			INT_IntEn_ADDR;
#define INT_MASK 0x10
#pragma	ioport	INT_MUXBusCtrl_ADDR:	0x1d9
BYTE			INT_MUXBusCtrl_ADDR;
// I2CSDA address and mask defines
#pragma	ioport	I2CSDA_Data_ADDR:	0x4
BYTE			I2CSDA_Data_ADDR;
#pragma	ioport	I2CSDA_DriveMode_0_ADDR:	0x104
BYTE			I2CSDA_DriveMode_0_ADDR;
#pragma	ioport	I2CSDA_DriveMode_1_ADDR:	0x105
BYTE			I2CSDA_DriveMode_1_ADDR;
#pragma	ioport	I2CSDA_DriveMode_2_ADDR:	0x7
BYTE			I2CSDA_DriveMode_2_ADDR;
#pragma	ioport	I2CSDA_GlobalSelect_ADDR:	0x6
BYTE			I2CSDA_GlobalSelect_ADDR;
#pragma	ioport	I2CSDA_IntCtrl_0_ADDR:	0x106
BYTE			I2CSDA_IntCtrl_0_ADDR;
#pragma	ioport	I2CSDA_IntCtrl_1_ADDR:	0x107
BYTE			I2CSDA_IntCtrl_1_ADDR;
#pragma	ioport	I2CSDA_IntEn_ADDR:	0x5
BYTE			I2CSDA_IntEn_ADDR;
#define I2CSDA_MASK 0x20
#pragma	ioport	I2CSDA_MUXBusCtrl_ADDR:	0x1d9
BYTE			I2CSDA_MUXBusCtrl_ADDR;
// A1 address and mask defines
#pragma	ioport	A1_Data_ADDR:	0x4
BYTE			A1_Data_ADDR;
#pragma	ioport	A1_DriveMode_0_ADDR:	0x104
BYTE			A1_DriveMode_0_ADDR;
#pragma	ioport	A1_DriveMode_1_ADDR:	0x105
BYTE			A1_DriveMode_1_ADDR;
#pragma	ioport	A1_DriveMode_2_ADDR:	0x7
BYTE			A1_DriveMode_2_ADDR;
#pragma	ioport	A1_GlobalSelect_ADDR:	0x6
BYTE			A1_GlobalSelect_ADDR;
#pragma	ioport	A1_IntCtrl_0_ADDR:	0x106
BYTE			A1_IntCtrl_0_ADDR;
#pragma	ioport	A1_IntCtrl_1_ADDR:	0x107
BYTE			A1_IntCtrl_1_ADDR;
#pragma	ioport	A1_IntEn_ADDR:	0x5
BYTE			A1_IntEn_ADDR;
#define A1_MASK 0x40
#pragma	ioport	A1_MUXBusCtrl_ADDR:	0x1d9
BYTE			A1_MUXBusCtrl_ADDR;
// I2CSCL address and mask defines
#pragma	ioport	I2CSCL_Data_ADDR:	0x4
BYTE			I2CSCL_Data_ADDR;
#pragma	ioport	I2CSCL_DriveMode_0_ADDR:	0x104
BYTE			I2CSCL_DriveMode_0_ADDR;
#pragma	ioport	I2CSCL_DriveMode_1_ADDR:	0x105
BYTE			I2CSCL_DriveMode_1_ADDR;
#pragma	ioport	I2CSCL_DriveMode_2_ADDR:	0x7
BYTE			I2CSCL_DriveMode_2_ADDR;
#pragma	ioport	I2CSCL_GlobalSelect_ADDR:	0x6
BYTE			I2CSCL_GlobalSelect_ADDR;
#pragma	ioport	I2CSCL_IntCtrl_0_ADDR:	0x106
BYTE			I2CSCL_IntCtrl_0_ADDR;
#pragma	ioport	I2CSCL_IntCtrl_1_ADDR:	0x107
BYTE			I2CSCL_IntCtrl_1_ADDR;
#pragma	ioport	I2CSCL_IntEn_ADDR:	0x5
BYTE			I2CSCL_IntEn_ADDR;
#define I2CSCL_MASK 0x80
#pragma	ioport	I2CSCL_MUXBusCtrl_ADDR:	0x1d9
BYTE			I2CSCL_MUXBusCtrl_ADDR;
// LED0 address and mask defines
#pragma	ioport	LED0_Data_ADDR:	0x8
BYTE			LED0_Data_ADDR;
#pragma	ioport	LED0_DriveMode_0_ADDR:	0x108
BYTE			LED0_DriveMode_0_ADDR;
#pragma	ioport	LED0_DriveMode_1_ADDR:	0x109
BYTE			LED0_DriveMode_1_ADDR;
#pragma	ioport	LED0_DriveMode_2_ADDR:	0xb
BYTE			LED0_DriveMode_2_ADDR;
#pragma	ioport	LED0_GlobalSelect_ADDR:	0xa
BYTE			LED0_GlobalSelect_ADDR;
#pragma	ioport	LED0_IntCtrl_0_ADDR:	0x10a
BYTE			LED0_IntCtrl_0_ADDR;
#pragma	ioport	LED0_IntCtrl_1_ADDR:	0x10b
BYTE			LED0_IntCtrl_1_ADDR;
#pragma	ioport	LED0_IntEn_ADDR:	0x9
BYTE			LED0_IntEn_ADDR;
#define LED0_MASK 0x1
#pragma	ioport	LED0_MUXBusCtrl_ADDR:	0x1da
BYTE			LED0_MUXBusCtrl_ADDR;
// LED1 address and mask defines
#pragma	ioport	LED1_Data_ADDR:	0x8
BYTE			LED1_Data_ADDR;
#pragma	ioport	LED1_DriveMode_0_ADDR:	0x108
BYTE			LED1_DriveMode_0_ADDR;
#pragma	ioport	LED1_DriveMode_1_ADDR:	0x109
BYTE			LED1_DriveMode_1_ADDR;
#pragma	ioport	LED1_DriveMode_2_ADDR:	0xb
BYTE			LED1_DriveMode_2_ADDR;
#pragma	ioport	LED1_GlobalSelect_ADDR:	0xa
BYTE			LED1_GlobalSelect_ADDR;
#pragma	ioport	LED1_IntCtrl_0_ADDR:	0x10a
BYTE			LED1_IntCtrl_0_ADDR;
#pragma	ioport	LED1_IntCtrl_1_ADDR:	0x10b
BYTE			LED1_IntCtrl_1_ADDR;
#pragma	ioport	LED1_IntEn_ADDR:	0x9
BYTE			LED1_IntEn_ADDR;
#define LED1_MASK 0x2
#pragma	ioport	LED1_MUXBusCtrl_ADDR:	0x1da
BYTE			LED1_MUXBusCtrl_ADDR;
// LED2 address and mask defines
#pragma	ioport	LED2_Data_ADDR:	0x8
BYTE			LED2_Data_ADDR;
#pragma	ioport	LED2_DriveMode_0_ADDR:	0x108
BYTE			LED2_DriveMode_0_ADDR;
#pragma	ioport	LED2_DriveMode_1_ADDR:	0x109
BYTE			LED2_DriveMode_1_ADDR;
#pragma	ioport	LED2_DriveMode_2_ADDR:	0xb
BYTE			LED2_DriveMode_2_ADDR;
#pragma	ioport	LED2_GlobalSelect_ADDR:	0xa
BYTE			LED2_GlobalSelect_ADDR;
#pragma	ioport	LED2_IntCtrl_0_ADDR:	0x10a
BYTE			LED2_IntCtrl_0_ADDR;
#pragma	ioport	LED2_IntCtrl_1_ADDR:	0x10b
BYTE			LED2_IntCtrl_1_ADDR;
#pragma	ioport	LED2_IntEn_ADDR:	0x9
BYTE			LED2_IntEn_ADDR;
#define LED2_MASK 0x4
#pragma	ioport	LED2_MUXBusCtrl_ADDR:	0x1da
BYTE			LED2_MUXBusCtrl_ADDR;
// LED3 address and mask defines
#pragma	ioport	LED3_Data_ADDR:	0x8
BYTE			LED3_Data_ADDR;
#pragma	ioport	LED3_DriveMode_0_ADDR:	0x108
BYTE			LED3_DriveMode_0_ADDR;
#pragma	ioport	LED3_DriveMode_1_ADDR:	0x109
BYTE			LED3_DriveMode_1_ADDR;
#pragma	ioport	LED3_DriveMode_2_ADDR:	0xb
BYTE			LED3_DriveMode_2_ADDR;
#pragma	ioport	LED3_GlobalSelect_ADDR:	0xa
BYTE			LED3_GlobalSelect_ADDR;
#pragma	ioport	LED3_IntCtrl_0_ADDR:	0x10a
BYTE			LED3_IntCtrl_0_ADDR;
#pragma	ioport	LED3_IntCtrl_1_ADDR:	0x10b
BYTE			LED3_IntCtrl_1_ADDR;
#pragma	ioport	LED3_IntEn_ADDR:	0x9
BYTE			LED3_IntEn_ADDR;
#define LED3_MASK 0x8
#pragma	ioport	LED3_MUXBusCtrl_ADDR:	0x1da
BYTE			LED3_MUXBusCtrl_ADDR;
// LED4 address and mask defines
#pragma	ioport	LED4_Data_ADDR:	0x8
BYTE			LED4_Data_ADDR;
#pragma	ioport	LED4_DriveMode_0_ADDR:	0x108
BYTE			LED4_DriveMode_0_ADDR;
#pragma	ioport	LED4_DriveMode_1_ADDR:	0x109
BYTE			LED4_DriveMode_1_ADDR;
#pragma	ioport	LED4_DriveMode_2_ADDR:	0xb
BYTE			LED4_DriveMode_2_ADDR;
#pragma	ioport	LED4_GlobalSelect_ADDR:	0xa
BYTE			LED4_GlobalSelect_ADDR;
#pragma	ioport	LED4_IntCtrl_0_ADDR:	0x10a
BYTE			LED4_IntCtrl_0_ADDR;
#pragma	ioport	LED4_IntCtrl_1_ADDR:	0x10b
BYTE			LED4_IntCtrl_1_ADDR;
#pragma	ioport	LED4_IntEn_ADDR:	0x9
BYTE			LED4_IntEn_ADDR;
#define LED4_MASK 0x10
#pragma	ioport	LED4_MUXBusCtrl_ADDR:	0x1da
BYTE			LED4_MUXBusCtrl_ADDR;
// LED5 address and mask defines
#pragma	ioport	LED5_Data_ADDR:	0x8
BYTE			LED5_Data_ADDR;
#pragma	ioport	LED5_DriveMode_0_ADDR:	0x108
BYTE			LED5_DriveMode_0_ADDR;
#pragma	ioport	LED5_DriveMode_1_ADDR:	0x109
BYTE			LED5_DriveMode_1_ADDR;
#pragma	ioport	LED5_DriveMode_2_ADDR:	0xb
BYTE			LED5_DriveMode_2_ADDR;
#pragma	ioport	LED5_GlobalSelect_ADDR:	0xa
BYTE			LED5_GlobalSelect_ADDR;
#pragma	ioport	LED5_IntCtrl_0_ADDR:	0x10a
BYTE			LED5_IntCtrl_0_ADDR;
#pragma	ioport	LED5_IntCtrl_1_ADDR:	0x10b
BYTE			LED5_IntCtrl_1_ADDR;
#pragma	ioport	LED5_IntEn_ADDR:	0x9
BYTE			LED5_IntEn_ADDR;
#define LED5_MASK 0x20
#pragma	ioport	LED5_MUXBusCtrl_ADDR:	0x1da
BYTE			LED5_MUXBusCtrl_ADDR;
// LED6 address and mask defines
#pragma	ioport	LED6_Data_ADDR:	0x8
BYTE			LED6_Data_ADDR;
#pragma	ioport	LED6_DriveMode_0_ADDR:	0x108
BYTE			LED6_DriveMode_0_ADDR;
#pragma	ioport	LED6_DriveMode_1_ADDR:	0x109
BYTE			LED6_DriveMode_1_ADDR;
#pragma	ioport	LED6_DriveMode_2_ADDR:	0xb
BYTE			LED6_DriveMode_2_ADDR;
#pragma	ioport	LED6_GlobalSelect_ADDR:	0xa
BYTE			LED6_GlobalSelect_ADDR;
#pragma	ioport	LED6_IntCtrl_0_ADDR:	0x10a
BYTE			LED6_IntCtrl_0_ADDR;
#pragma	ioport	LED6_IntCtrl_1_ADDR:	0x10b
BYTE			LED6_IntCtrl_1_ADDR;
#pragma	ioport	LED6_IntEn_ADDR:	0x9
BYTE			LED6_IntEn_ADDR;
#define LED6_MASK 0x40
#pragma	ioport	LED6_MUXBusCtrl_ADDR:	0x1da
BYTE			LED6_MUXBusCtrl_ADDR;
// LED7 address and mask defines
#pragma	ioport	LED7_Data_ADDR:	0x8
BYTE			LED7_Data_ADDR;
#pragma	ioport	LED7_DriveMode_0_ADDR:	0x108
BYTE			LED7_DriveMode_0_ADDR;
#pragma	ioport	LED7_DriveMode_1_ADDR:	0x109
BYTE			LED7_DriveMode_1_ADDR;
#pragma	ioport	LED7_DriveMode_2_ADDR:	0xb
BYTE			LED7_DriveMode_2_ADDR;
#pragma	ioport	LED7_GlobalSelect_ADDR:	0xa
BYTE			LED7_GlobalSelect_ADDR;
#pragma	ioport	LED7_IntCtrl_0_ADDR:	0x10a
BYTE			LED7_IntCtrl_0_ADDR;
#pragma	ioport	LED7_IntCtrl_1_ADDR:	0x10b
BYTE			LED7_IntCtrl_1_ADDR;
#pragma	ioport	LED7_IntEn_ADDR:	0x9
BYTE			LED7_IntEn_ADDR;
#define LED7_MASK 0x80
#pragma	ioport	LED7_MUXBusCtrl_ADDR:	0x1da
BYTE			LED7_MUXBusCtrl_ADDR;