psocgpioint.h

cypress的触摸按键模块介绍calibrating_capsense_with_the_csr_user_module___an2355_13.

// SENSESW0 address and mask defines
#pragma	ioport	SENSESW0_Data_ADDR:	0x0
BYTE			SENSESW0_Data_ADDR;
#pragma	ioport	SENSESW0_DriveMode_0_ADDR:	0x100
BYTE			SENSESW0_DriveMode_0_ADDR;
#pragma	ioport	SENSESW0_DriveMode_1_ADDR:	0x101
BYTE			SENSESW0_DriveMode_1_ADDR;
#pragma	ioport	SENSESW0_DriveMode_2_ADDR:	0x3
BYTE			SENSESW0_DriveMode_2_ADDR;
#pragma	ioport	SENSESW0_GlobalSelect_ADDR:	0x2
BYTE			SENSESW0_GlobalSelect_ADDR;
#pragma	ioport	SENSESW0_IntCtrl_0_ADDR:	0x102
BYTE			SENSESW0_IntCtrl_0_ADDR;
#pragma	ioport	SENSESW0_IntCtrl_1_ADDR:	0x103
BYTE			SENSESW0_IntCtrl_1_ADDR;
#pragma	ioport	SENSESW0_IntEn_ADDR:	0x1
BYTE			SENSESW0_IntEn_ADDR;
#define SENSESW0_MASK 0x1
#pragma	ioport	SENSESW0_MUXBusCtrl_ADDR:	0x1d8
BYTE			SENSESW0_MUXBusCtrl_ADDR;
// SENSESW0 Shadow defines
//   SENSESW0_DataShadow define
extern BYTE Port_0_Data_SHADE;
#define SENSESW0_DataShadow (*(unsigned char*)&Port_0_Data_SHADE)
// SENSESW1 address and mask defines
#pragma	ioport	SENSESW1_Data_ADDR:	0x0
BYTE			SENSESW1_Data_ADDR;
#pragma	ioport	SENSESW1_DriveMode_0_ADDR:	0x100
BYTE			SENSESW1_DriveMode_0_ADDR;
#pragma	ioport	SENSESW1_DriveMode_1_ADDR:	0x101
BYTE			SENSESW1_DriveMode_1_ADDR;
#pragma	ioport	SENSESW1_DriveMode_2_ADDR:	0x3
BYTE			SENSESW1_DriveMode_2_ADDR;
#pragma	ioport	SENSESW1_GlobalSelect_ADDR:	0x2
BYTE			SENSESW1_GlobalSelect_ADDR;
#pragma	ioport	SENSESW1_IntCtrl_0_ADDR:	0x102
BYTE			SENSESW1_IntCtrl_0_ADDR;
#pragma	ioport	SENSESW1_IntCtrl_1_ADDR:	0x103
BYTE			SENSESW1_IntCtrl_1_ADDR;
#pragma	ioport	SENSESW1_IntEn_ADDR:	0x1
BYTE			SENSESW1_IntEn_ADDR;
#define SENSESW1_MASK 0x2
#pragma	ioport	SENSESW1_MUXBusCtrl_ADDR:	0x1d8
BYTE			SENSESW1_MUXBusCtrl_ADDR;
// SENSESW1 Shadow defines
//   SENSESW1_DataShadow define
extern BYTE Port_0_Data_SHADE;
#define SENSESW1_DataShadow (*(unsigned char*)&Port_0_Data_SHADE)
// SENSESW2 address and mask defines
#pragma	ioport	SENSESW2_Data_ADDR:	0x0
BYTE			SENSESW2_Data_ADDR;
#pragma	ioport	SENSESW2_DriveMode_0_ADDR:	0x100
BYTE			SENSESW2_DriveMode_0_ADDR;
#pragma	ioport	SENSESW2_DriveMode_1_ADDR:	0x101
BYTE			SENSESW2_DriveMode_1_ADDR;
#pragma	ioport	SENSESW2_DriveMode_2_ADDR:	0x3
BYTE			SENSESW2_DriveMode_2_ADDR;
#pragma	ioport	SENSESW2_GlobalSelect_ADDR:	0x2
BYTE			SENSESW2_GlobalSelect_ADDR;
#pragma	ioport	SENSESW2_IntCtrl_0_ADDR:	0x102
BYTE			SENSESW2_IntCtrl_0_ADDR;
#pragma	ioport	SENSESW2_IntCtrl_1_ADDR:	0x103
BYTE			SENSESW2_IntCtrl_1_ADDR;
#pragma	ioport	SENSESW2_IntEn_ADDR:	0x1
BYTE			SENSESW2_IntEn_ADDR;
#define SENSESW2_MASK 0x4
#pragma	ioport	SENSESW2_MUXBusCtrl_ADDR:	0x1d8
BYTE			SENSESW2_MUXBusCtrl_ADDR;
// SENSESW2 Shadow defines
//   SENSESW2_DataShadow define
extern BYTE Port_0_Data_SHADE;
#define SENSESW2_DataShadow (*(unsigned char*)&Port_0_Data_SHADE)
// SENSESW3 address and mask defines
#pragma	ioport	SENSESW3_Data_ADDR:	0x0
BYTE			SENSESW3_Data_ADDR;
#pragma	ioport	SENSESW3_DriveMode_0_ADDR:	0x100
BYTE			SENSESW3_DriveMode_0_ADDR;
#pragma	ioport	SENSESW3_DriveMode_1_ADDR:	0x101
BYTE			SENSESW3_DriveMode_1_ADDR;
#pragma	ioport	SENSESW3_DriveMode_2_ADDR:	0x3
BYTE			SENSESW3_DriveMode_2_ADDR;
#pragma	ioport	SENSESW3_GlobalSelect_ADDR:	0x2
BYTE			SENSESW3_GlobalSelect_ADDR;
#pragma	ioport	SENSESW3_IntCtrl_0_ADDR:	0x102
BYTE			SENSESW3_IntCtrl_0_ADDR;
#pragma	ioport	SENSESW3_IntCtrl_1_ADDR:	0x103
BYTE			SENSESW3_IntCtrl_1_ADDR;
#pragma	ioport	SENSESW3_IntEn_ADDR:	0x1
BYTE			SENSESW3_IntEn_ADDR;
#define SENSESW3_MASK 0x8
#pragma	ioport	SENSESW3_MUXBusCtrl_ADDR:	0x1d8
BYTE			SENSESW3_MUXBusCtrl_ADDR;
// SENSESW3 Shadow defines
//   SENSESW3_DataShadow define
extern BYTE Port_0_Data_SHADE;
#define SENSESW3_DataShadow (*(unsigned char*)&Port_0_Data_SHADE)
// SENSESW4 address and mask defines
#pragma	ioport	SENSESW4_Data_ADDR:	0x0
BYTE			SENSESW4_Data_ADDR;
#pragma	ioport	SENSESW4_DriveMode_0_ADDR:	0x100
BYTE			SENSESW4_DriveMode_0_ADDR;
#pragma	ioport	SENSESW4_DriveMode_1_ADDR:	0x101
BYTE			SENSESW4_DriveMode_1_ADDR;
#pragma	ioport	SENSESW4_DriveMode_2_ADDR:	0x3
BYTE			SENSESW4_DriveMode_2_ADDR;
#pragma	ioport	SENSESW4_GlobalSelect_ADDR:	0x2
BYTE			SENSESW4_GlobalSelect_ADDR;
#pragma	ioport	SENSESW4_IntCtrl_0_ADDR:	0x102
BYTE			SENSESW4_IntCtrl_0_ADDR;
#pragma	ioport	SENSESW4_IntCtrl_1_ADDR:	0x103
BYTE			SENSESW4_IntCtrl_1_ADDR;
#pragma	ioport	SENSESW4_IntEn_ADDR:	0x1
BYTE			SENSESW4_IntEn_ADDR;
#define SENSESW4_MASK 0x10
#pragma	ioport	SENSESW4_MUXBusCtrl_ADDR:	0x1d8
BYTE			SENSESW4_MUXBusCtrl_ADDR;
// SENSESW4 Shadow defines
//   SENSESW4_DataShadow define
extern BYTE Port_0_Data_SHADE;
#define SENSESW4_DataShadow (*(unsigned char*)&Port_0_Data_SHADE)
// SENSESW5 address and mask defines
#pragma	ioport	SENSESW5_Data_ADDR:	0x0
BYTE			SENSESW5_Data_ADDR;
#pragma	ioport	SENSESW5_DriveMode_0_ADDR:	0x100
BYTE			SENSESW5_DriveMode_0_ADDR;
#pragma	ioport	SENSESW5_DriveMode_1_ADDR:	0x101
BYTE			SENSESW5_DriveMode_1_ADDR;
#pragma	ioport	SENSESW5_DriveMode_2_ADDR:	0x3
BYTE			SENSESW5_DriveMode_2_ADDR;
#pragma	ioport	SENSESW5_GlobalSelect_ADDR:	0x2
BYTE			SENSESW5_GlobalSelect_ADDR;
#pragma	ioport	SENSESW5_IntCtrl_0_ADDR:	0x102
BYTE			SENSESW5_IntCtrl_0_ADDR;
#pragma	ioport	SENSESW5_IntCtrl_1_ADDR:	0x103
BYTE			SENSESW5_IntCtrl_1_ADDR;
#pragma	ioport	SENSESW5_IntEn_ADDR:	0x1
BYTE			SENSESW5_IntEn_ADDR;
#define SENSESW5_MASK 0x20
#pragma	ioport	SENSESW5_MUXBusCtrl_ADDR:	0x1d8
BYTE			SENSESW5_MUXBusCtrl_ADDR;
// SENSESW5 Shadow defines
//   SENSESW5_DataShadow define
extern BYTE Port_0_Data_SHADE;
#define SENSESW5_DataShadow (*(unsigned char*)&Port_0_Data_SHADE)
// SENSESW6 address and mask defines
#pragma	ioport	SENSESW6_Data_ADDR:	0x0
BYTE			SENSESW6_Data_ADDR;
#pragma	ioport	SENSESW6_DriveMode_0_ADDR:	0x100
BYTE			SENSESW6_DriveMode_0_ADDR;
#pragma	ioport	SENSESW6_DriveMode_1_ADDR:	0x101
BYTE			SENSESW6_DriveMode_1_ADDR;
#pragma	ioport	SENSESW6_DriveMode_2_ADDR:	0x3
BYTE			SENSESW6_DriveMode_2_ADDR;
#pragma	ioport	SENSESW6_GlobalSelect_ADDR:	0x2
BYTE			SENSESW6_GlobalSelect_ADDR;
#pragma	ioport	SENSESW6_IntCtrl_0_ADDR:	0x102
BYTE			SENSESW6_IntCtrl_0_ADDR;
#pragma	ioport	SENSESW6_IntCtrl_1_ADDR:	0x103
BYTE			SENSESW6_IntCtrl_1_ADDR;
#pragma	ioport	SENSESW6_IntEn_ADDR:	0x1
BYTE			SENSESW6_IntEn_ADDR;
#define SENSESW6_MASK 0x40
#pragma	ioport	SENSESW6_MUXBusCtrl_ADDR:	0x1d8
BYTE			SENSESW6_MUXBusCtrl_ADDR;
// SENSESW6 Shadow defines
//   SENSESW6_DataShadow define
extern BYTE Port_0_Data_SHADE;
#define SENSESW6_DataShadow (*(unsigned char*)&Port_0_Data_SHADE)
// SENSESW7 address and mask defines
#pragma	ioport	SENSESW7_Data_ADDR:	0x0
BYTE			SENSESW7_Data_ADDR;
#pragma	ioport	SENSESW7_DriveMode_0_ADDR:	0x100
BYTE			SENSESW7_DriveMode_0_ADDR;
#pragma	ioport	SENSESW7_DriveMode_1_ADDR:	0x101
BYTE			SENSESW7_DriveMode_1_ADDR;
#pragma	ioport	SENSESW7_DriveMode_2_ADDR:	0x3
BYTE			SENSESW7_DriveMode_2_ADDR;
#pragma	ioport	SENSESW7_GlobalSelect_ADDR:	0x2
BYTE			SENSESW7_GlobalSelect_ADDR;
#pragma	ioport	SENSESW7_IntCtrl_0_ADDR:	0x102
BYTE			SENSESW7_IntCtrl_0_ADDR;
#pragma	ioport	SENSESW7_IntCtrl_1_ADDR:	0x103
BYTE			SENSESW7_IntCtrl_1_ADDR;
#pragma	ioport	SENSESW7_IntEn_ADDR:	0x1
BYTE			SENSESW7_IntEn_ADDR;
#define SENSESW7_MASK 0x80
#pragma	ioport	SENSESW7_MUXBusCtrl_ADDR:	0x1d8
BYTE			SENSESW7_MUXBusCtrl_ADDR;
// SENSESW7 Shadow defines
//   SENSESW7_DataShadow define
extern BYTE Port_0_Data_SHADE;
#define SENSESW7_DataShadow (*(unsigned char*)&Port_0_Data_SHADE)
// A0 address and mask defines
#pragma	ioport	A0_Data_ADDR:	0x4
BYTE			A0_Data_ADDR;
#pragma	ioport	A0_DriveMode_0_ADDR:	0x104
BYTE			A0_DriveMode_0_ADDR;
#pragma	ioport	A0_DriveMode_1_ADDR:	0x105
BYTE			A0_DriveMode_1_ADDR;
#pragma	ioport	A0_DriveMode_2_ADDR:	0x7
BYTE			A0_DriveMode_2_ADDR;
#pragma	ioport	A0_GlobalSelect_ADDR:	0x6
BYTE			A0_GlobalSelect_ADDR;
#pragma	ioport	A0_IntCtrl_0_ADDR:	0x106
BYTE			A0_IntCtrl_0_ADDR;
#pragma	ioport	A0_IntCtrl_1_ADDR:	0x107
BYTE			A0_IntCtrl_1_ADDR;
#pragma	ioport	A0_IntEn_ADDR:	0x5
BYTE			A0_IntEn_ADDR;
#define A0_MASK 0x8
#pragma	ioport	A0_MUXBusCtrl_ADDR:	0x1d9
BYTE			A0_MUXBusCtrl_ADDR;
// INT address and mask defines
#pragma	ioport	INT_Data_ADDR:	0x4
BYTE			INT_Data_ADDR;
#pragma	ioport	INT_DriveMode_0_ADDR:	0x104
BYTE			INT_DriveMode_0_ADDR;
#pragma	ioport	INT_DriveMode_1_ADDR:	0x105
BYTE			INT_DriveMode_1_ADDR;
#pragma	ioport	INT_DriveMode_2_ADDR:	0x7
BYTE			INT_DriveMode_2_ADDR;
#pragma	ioport	INT_GlobalSelect_ADDR:	0x6
BYTE			INT_GlobalSelect_ADDR;
#pragma	ioport	INT_IntCtrl_0_ADDR:	0x106
BYTE			INT_IntCtrl_0_ADDR;
#pragma	ioport	INT_IntCtrl_1_ADDR:	0x107
BYTE			INT_IntCtrl_1_ADDR;