psocgpioint.inc

cypress的触摸按键模块介绍calibrating_capsense_with_the_csr_user_module___an2355_13.

; SENSESW0 address and mask equates
SENSESW0_Data_ADDR:	equ	0h
SENSESW0_DriveMode_0_ADDR:	equ	100h
SENSESW0_DriveMode_1_ADDR:	equ	101h
SENSESW0_DriveMode_2_ADDR:	equ	3h
SENSESW0_GlobalSelect_ADDR:	equ	2h
SENSESW0_IntCtrl_0_ADDR:	equ	102h
SENSESW0_IntCtrl_1_ADDR:	equ	103h
SENSESW0_IntEn_ADDR:	equ	1h
SENSESW0_MASK:	equ	1h
SENSESW0_MUXBusCtrl_ADDR:	equ	1d8h
; SENSESW0_Data access macros
;   GetSENSESW0_Data macro, return in a
macro GetSENSESW0_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 1h
endm
;   SetSENSESW0_Data macro
macro SetSENSESW0_Data
	or		[Port_0_Data_SHADE], 1h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetSENSESW0_Data macro
macro ClearSENSESW0_Data
	and		[Port_0_Data_SHADE], ~1h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm

; SENSESW1 address and mask equates
SENSESW1_Data_ADDR:	equ	0h
SENSESW1_DriveMode_0_ADDR:	equ	100h
SENSESW1_DriveMode_1_ADDR:	equ	101h
SENSESW1_DriveMode_2_ADDR:	equ	3h
SENSESW1_GlobalSelect_ADDR:	equ	2h
SENSESW1_IntCtrl_0_ADDR:	equ	102h
SENSESW1_IntCtrl_1_ADDR:	equ	103h
SENSESW1_IntEn_ADDR:	equ	1h
SENSESW1_MASK:	equ	2h
SENSESW1_MUXBusCtrl_ADDR:	equ	1d8h
; SENSESW1_Data access macros
;   GetSENSESW1_Data macro, return in a
macro GetSENSESW1_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 2h
endm
;   SetSENSESW1_Data macro
macro SetSENSESW1_Data
	or		[Port_0_Data_SHADE], 2h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetSENSESW1_Data macro
macro ClearSENSESW1_Data
	and		[Port_0_Data_SHADE], ~2h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm

; SENSESW2 address and mask equates
SENSESW2_Data_ADDR:	equ	0h
SENSESW2_DriveMode_0_ADDR:	equ	100h
SENSESW2_DriveMode_1_ADDR:	equ	101h
SENSESW2_DriveMode_2_ADDR:	equ	3h
SENSESW2_GlobalSelect_ADDR:	equ	2h
SENSESW2_IntCtrl_0_ADDR:	equ	102h
SENSESW2_IntCtrl_1_ADDR:	equ	103h
SENSESW2_IntEn_ADDR:	equ	1h
SENSESW2_MASK:	equ	4h
SENSESW2_MUXBusCtrl_ADDR:	equ	1d8h
; SENSESW2_Data access macros
;   GetSENSESW2_Data macro, return in a
macro GetSENSESW2_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 4h
endm
;   SetSENSESW2_Data macro
macro SetSENSESW2_Data
	or		[Port_0_Data_SHADE], 4h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetSENSESW2_Data macro
macro ClearSENSESW2_Data
	and		[Port_0_Data_SHADE], ~4h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm

; SENSESW3 address and mask equates
SENSESW3_Data_ADDR:	equ	0h
SENSESW3_DriveMode_0_ADDR:	equ	100h
SENSESW3_DriveMode_1_ADDR:	equ	101h
SENSESW3_DriveMode_2_ADDR:	equ	3h
SENSESW3_GlobalSelect_ADDR:	equ	2h
SENSESW3_IntCtrl_0_ADDR:	equ	102h
SENSESW3_IntCtrl_1_ADDR:	equ	103h
SENSESW3_IntEn_ADDR:	equ	1h
SENSESW3_MASK:	equ	8h
SENSESW3_MUXBusCtrl_ADDR:	equ	1d8h
; SENSESW3_Data access macros
;   GetSENSESW3_Data macro, return in a
macro GetSENSESW3_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 8h
endm
;   SetSENSESW3_Data macro
macro SetSENSESW3_Data
	or		[Port_0_Data_SHADE], 8h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetSENSESW3_Data macro
macro ClearSENSESW3_Data
	and		[Port_0_Data_SHADE], ~8h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm

; SENSESW4 address and mask equates
SENSESW4_Data_ADDR:	equ	0h
SENSESW4_DriveMode_0_ADDR:	equ	100h
SENSESW4_DriveMode_1_ADDR:	equ	101h
SENSESW4_DriveMode_2_ADDR:	equ	3h
SENSESW4_GlobalSelect_ADDR:	equ	2h
SENSESW4_IntCtrl_0_ADDR:	equ	102h
SENSESW4_IntCtrl_1_ADDR:	equ	103h
SENSESW4_IntEn_ADDR:	equ	1h
SENSESW4_MASK:	equ	10h
SENSESW4_MUXBusCtrl_ADDR:	equ	1d8h
; SENSESW4_Data access macros
;   GetSENSESW4_Data macro, return in a
macro GetSENSESW4_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 10h
endm
;   SetSENSESW4_Data macro
macro SetSENSESW4_Data
	or		[Port_0_Data_SHADE], 10h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetSENSESW4_Data macro
macro ClearSENSESW4_Data
	and		[Port_0_Data_SHADE], ~10h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm

; SENSESW5 address and mask equates
SENSESW5_Data_ADDR:	equ	0h
SENSESW5_DriveMode_0_ADDR:	equ	100h
SENSESW5_DriveMode_1_ADDR:	equ	101h
SENSESW5_DriveMode_2_ADDR:	equ	3h
SENSESW5_GlobalSelect_ADDR:	equ	2h
SENSESW5_IntCtrl_0_ADDR:	equ	102h
SENSESW5_IntCtrl_1_ADDR:	equ	103h
SENSESW5_IntEn_ADDR:	equ	1h
SENSESW5_MASK:	equ	20h
SENSESW5_MUXBusCtrl_ADDR:	equ	1d8h
; SENSESW5_Data access macros
;   GetSENSESW5_Data macro, return in a
macro GetSENSESW5_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 20h
endm
;   SetSENSESW5_Data macro
macro SetSENSESW5_Data
	or		[Port_0_Data_SHADE], 20h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetSENSESW5_Data macro
macro ClearSENSESW5_Data
	and		[Port_0_Data_SHADE], ~20h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm

; SENSESW6 address and mask equates
SENSESW6_Data_ADDR:	equ	0h
SENSESW6_DriveMode_0_ADDR:	equ	100h
SENSESW6_DriveMode_1_ADDR:	equ	101h
SENSESW6_DriveMode_2_ADDR:	equ	3h
SENSESW6_GlobalSelect_ADDR:	equ	2h
SENSESW6_IntCtrl_0_ADDR:	equ	102h
SENSESW6_IntCtrl_1_ADDR:	equ	103h
SENSESW6_IntEn_ADDR:	equ	1h
SENSESW6_MASK:	equ	40h
SENSESW6_MUXBusCtrl_ADDR:	equ	1d8h
; SENSESW6_Data access macros
;   GetSENSESW6_Data macro, return in a
macro GetSENSESW6_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 40h
endm
;   SetSENSESW6_Data macro
macro SetSENSESW6_Data
	or		[Port_0_Data_SHADE], 40h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetSENSESW6_Data macro
macro ClearSENSESW6_Data
	and		[Port_0_Data_SHADE], ~40h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm

; SENSESW7 address and mask equates
SENSESW7_Data_ADDR:	equ	0h
SENSESW7_DriveMode_0_ADDR:	equ	100h
SENSESW7_DriveMode_1_ADDR:	equ	101h
SENSESW7_DriveMode_2_ADDR:	equ	3h
SENSESW7_GlobalSelect_ADDR:	equ	2h
SENSESW7_IntCtrl_0_ADDR:	equ	102h
SENSESW7_IntCtrl_1_ADDR:	equ	103h
SENSESW7_IntEn_ADDR:	equ	1h
SENSESW7_MASK:	equ	80h
SENSESW7_MUXBusCtrl_ADDR:	equ	1d8h
; SENSESW7_Data access macros
;   GetSENSESW7_Data macro, return in a
macro GetSENSESW7_Data
	mov		a,[Port_0_Data_SHADE]
	and		a, 80h
endm
;   SetSENSESW7_Data macro
macro SetSENSESW7_Data
	or		[Port_0_Data_SHADE], 80h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm
;   SetSENSESW7_Data macro
macro ClearSENSESW7_Data
	and		[Port_0_Data_SHADE], ~80h
	mov		reg[Port_0_Data], [Port_0_Data_SHADE]
endm

; A0 address and mask equates
A0_Data_ADDR:	equ	4h
A0_DriveMode_0_ADDR:	equ	104h
A0_DriveMode_1_ADDR:	equ	105h
A0_DriveMode_2_ADDR:	equ	7h
A0_GlobalSelect_ADDR:	equ	6h
A0_IntCtrl_0_ADDR:	equ	106h
A0_IntCtrl_1_ADDR:	equ	107h
A0_IntEn_ADDR:	equ	5h
A0_MASK:	equ	8h
A0_MUXBusCtrl_ADDR:	equ	1d9h
; INT address and mask equates
INT_Data_ADDR:	equ	4h
INT_DriveMode_0_ADDR:	equ	104h
INT_DriveMode_1_ADDR:	equ	105h
INT_DriveMode_2_ADDR:	equ	7h
INT_GlobalSelect_ADDR:	equ	6h
INT_IntCtrl_0_ADDR:	equ	106h
INT_IntCtrl_1_ADDR:	equ	107h
INT_IntEn_ADDR:	equ	5h
INT_MASK:	equ	10h
INT_MUXBusCtrl_ADDR:	equ	1d9h
; I2CSDA address and mask equates
I2CSDA_Data_ADDR:	equ	4h
I2CSDA_DriveMode_0_ADDR:	equ	104h
I2CSDA_DriveMode_1_ADDR:	equ	105h
I2CSDA_DriveMode_2_ADDR:	equ	7h
I2CSDA_GlobalSelect_ADDR:	equ	6h
I2CSDA_IntCtrl_0_ADDR:	equ	106h
I2CSDA_IntCtrl_1_ADDR:	equ	107h
I2CSDA_IntEn_ADDR:	equ	5h
I2CSDA_MASK:	equ	20h
I2CSDA_MUXBusCtrl_ADDR:	equ	1d9h
; A1 address and mask equates
A1_Data_ADDR:	equ	4h
A1_DriveMode_0_ADDR:	equ	104h
A1_DriveMode_1_ADDR:	equ	105h
A1_DriveMode_2_ADDR:	equ	7h
A1_GlobalSelect_ADDR:	equ	6h
A1_IntCtrl_0_ADDR:	equ	106h
A1_IntCtrl_1_ADDR:	equ	107h
A1_IntEn_ADDR:	equ	5h
A1_MASK:	equ	40h
A1_MUXBusCtrl_ADDR:	equ	1d9h
; I2CSCL address and mask equates
I2CSCL_Data_ADDR:	equ	4h
I2CSCL_DriveMode_0_ADDR:	equ	104h
I2CSCL_DriveMode_1_ADDR:	equ	105h
I2CSCL_DriveMode_2_ADDR:	equ	7h
I2CSCL_GlobalSelect_ADDR:	equ	6h
I2CSCL_IntCtrl_0_ADDR:	equ	106h
I2CSCL_IntCtrl_1_ADDR:	equ	107h
I2CSCL_IntEn_ADDR:	equ	5h
I2CSCL_MASK:	equ	80h
I2CSCL_MUXBusCtrl_ADDR:	equ	1d9h
; LED0 address and mask equates
LED0_Data_ADDR:	equ	8h
LED0_DriveMode_0_ADDR:	equ	108h
LED0_DriveMode_1_ADDR:	equ	109h
LED0_DriveMode_2_ADDR:	equ	bh
LED0_GlobalSelect_ADDR:	equ	ah
LED0_IntCtrl_0_ADDR:	equ	10ah
LED0_IntCtrl_1_ADDR:	equ	10bh
LED0_IntEn_ADDR:	equ	9h
LED0_MASK:	equ	1h
LED0_MUXBusCtrl_ADDR:	equ	1dah
; LED1 address and mask equates
LED1_Data_ADDR:	equ	8h
LED1_DriveMode_0_ADDR:	equ	108h
LED1_DriveMode_1_ADDR:	equ	109h
LED1_DriveMode_2_ADDR:	equ	bh
LED1_GlobalSelect_ADDR:	equ	ah
LED1_IntCtrl_0_ADDR:	equ	10ah
LED1_IntCtrl_1_ADDR:	equ	10bh
LED1_IntEn_ADDR:	equ	9h
LED1_MASK:	equ	2h
LED1_MUXBusCtrl_ADDR:	equ	1dah
; LED2 address and mask equates
LED2_Data_ADDR:	equ	8h
LED2_DriveMode_0_ADDR:	equ	108h
LED2_DriveMode_1_ADDR:	equ	109h
LED2_DriveMode_2_ADDR:	equ	bh
LED2_GlobalSelect_ADDR:	equ	ah
LED2_IntCtrl_0_ADDR:	equ	10ah
LED2_IntCtrl_1_ADDR:	equ	10bh
LED2_IntEn_ADDR:	equ	9h
LED2_MASK:	equ	4h
LED2_MUXBusCtrl_ADDR:	equ	1dah
; LED3 address and mask equates
LED3_Data_ADDR:	equ	8h
LED3_DriveMode_0_ADDR:	equ	108h
LED3_DriveMode_1_ADDR:	equ	109h
LED3_DriveMode_2_ADDR:	equ	bh
LED3_GlobalSelect_ADDR:	equ	ah
LED3_IntCtrl_0_ADDR:	equ	10ah
LED3_IntCtrl_1_ADDR:	equ	10bh
LED3_IntEn_ADDR:	equ	9h
LED3_MASK:	equ	8h
LED3_MUXBusCtrl_ADDR:	equ	1dah
; LED4 address and mask equates
LED4_Data_ADDR:	equ	8h
LED4_DriveMode_0_ADDR:	equ	108h
LED4_DriveMode_1_ADDR:	equ	109h
LED4_DriveMode_2_ADDR:	equ	bh
LED4_GlobalSelect_ADDR:	equ	ah
LED4_IntCtrl_0_ADDR:	equ	10ah
LED4_IntCtrl_1_ADDR:	equ	10bh
LED4_IntEn_ADDR:	equ	9h
LED4_MASK:	equ	10h
LED4_MUXBusCtrl_ADDR:	equ	1dah
; LED5 address and mask equates
LED5_Data_ADDR:	equ	8h
LED5_DriveMode_0_ADDR:	equ	108h
LED5_DriveMode_1_ADDR:	equ	109h
LED5_DriveMode_2_ADDR:	equ	bh
LED5_GlobalSelect_ADDR:	equ	ah
LED5_IntCtrl_0_ADDR:	equ	10ah
LED5_IntCtrl_1_ADDR:	equ	10bh
LED5_IntEn_ADDR:	equ	9h
LED5_MASK:	equ	20h
LED5_MUXBusCtrl_ADDR:	equ	1dah
; LED6 address and mask equates
LED6_Data_ADDR:	equ	8h
LED6_DriveMode_0_ADDR:	equ	108h
LED6_DriveMode_1_ADDR:	equ	109h
LED6_DriveMode_2_ADDR:	equ	bh
LED6_GlobalSelect_ADDR:	equ	ah
LED6_IntCtrl_0_ADDR:	equ	10ah
LED6_IntCtrl_1_ADDR:	equ	10bh
LED6_IntEn_ADDR:	equ	9h
LED6_MASK:	equ	40h
LED6_MUXBusCtrl_ADDR:	equ	1dah
; LED7 address and mask equates
LED7_Data_ADDR:	equ	8h
LED7_DriveMode_0_ADDR:	equ	108h
LED7_DriveMode_1_ADDR:	equ	109h
LED7_DriveMode_2_ADDR:	equ	bh
LED7_GlobalSelect_ADDR:	equ	ah
LED7_IntCtrl_0_ADDR:	equ	10ah
LED7_IntCtrl_1_ADDR:	equ	10bh
LED7_IntEn_ADDR:	equ	9h
LED7_MASK:	equ	80h
LED7_MUXBusCtrl_ADDR:	equ	1dah