ezw_512.v

EZW Embedded Zero-tree Wavelets Encoding,video codecs from the EZW family which use a 3D version of

		5'b01100:reg_flag=5'b00101;
		
		5'b01101:reg_flag=5'b01001;
		5'b01110:reg_flag=5'b01001;
		5'b01111:reg_flag=5'b01001;
		5'b10000:reg_flag=5'b01001;
		
		5'b10001:reg_flag=5'b10001;
		5'b10010:reg_flag=5'b10001;
		5'b10011:reg_flag=5'b10001;
		5'b10100:reg_flag=5'b10001;
		default: reg_flag=5'b00000;
		endcase
	end
	else
		reg_flag=5'b00000;
end

always @(posedge clk)//negedge
begin
	if(!reset || !ready) begin
		iz_flag=5'b00000;
		
	end
	else begin
		if(posedge_counter==5'h0)begin//20
			iz_flag=reg_flag;
		end
		else begin
			if(counter==5'b00000)
				iz_flag=iz_flag | reg_flag;
			else
				iz_flag=iz_flag;
		end
	end
end

endmodule


module bitplane_reg(clk,reset,ready,counter_flag,negedge_counter,In_SMAP_data,In_SAQ_data,In_SAQ_counter,In_IZ_flag,Out_SMAP_data,Out_SAQ_data,Out_SAQ_counter,Out_IZ_flag);
input		clk,reset,ready;
input		counter_flag;
input	[4:0]	negedge_counter;
input	[41:0]	In_SMAP_data;
input	[20:0]	In_SAQ_data;
input	[4:0]	In_SAQ_counter,In_IZ_flag;

output	[41:0]	Out_SMAP_data;
output	[20:0]	Out_SAQ_data;
output	[4:0]	Out_SAQ_counter,Out_IZ_flag;

reg	[41:0]	Out_SMAP_data;
reg	[20:0]	Out_SAQ_data;
reg	[4:0]	Out_SAQ_counter,Out_IZ_flag;

always @(posedge clk)
begin
	if(!reset || !ready) begin
		Out_SMAP_data=42'h00000000000;
		Out_SAQ_data=21'h000000;
		Out_SAQ_counter=5'h00;
		Out_IZ_flag=5'h00;
	end
	else begin
		if(negedge_counter==5'h14 && counter_flag) begin
			Out_SMAP_data=In_SMAP_data;
			Out_SAQ_data=In_SAQ_data;
			Out_SAQ_counter=In_SAQ_counter;
			Out_IZ_flag=In_IZ_flag;
		end
		else begin
			Out_SMAP_data=Out_SMAP_data;
			Out_SAQ_data=Out_SAQ_data;
			Out_SAQ_counter=Out_SAQ_counter;
			Out_IZ_flag=Out_IZ_flag;
		end
	end
end
endmodule


module address_generator(clk,reset,ready,initial_pass,counter_flag,address,posedge_counter,negedge_counter,counter,Done);

parameter	size=512;

input		clk,reset,ready,initial_pass,counter_flag;

output	[17:0]	address;
output	[4:0]	posedge_counter,negedge_counter;
output	[17:0]	counter;
output	[1:0]	Done;

reg	[4:0]	posedge_counter,negedge_counter,initial_counter;
reg	[4:0]	address_counter;
reg	[17:0]	address,z_addr;
reg	[17:0]	counter;
reg	[1:0]	Done;

always @(negedge clk)//posedge
begin
	if(!reset  || !ready)
		address_counter=0;
	else
		if(address_counter==5'h14)
			address_counter=0;
		else
			if(address_counter==5'h00)
				if(counter_flag)
					address_counter=address_counter+1'b1;
				else
					address_counter=address_counter;
			else
				address_counter=address_counter+1'b1;
end

always @(negedge clk)
begin
	if(!reset ||!ready)begin
		counter=(size/8*size/8);
		
	end
	else
		if((address_counter==5'h14) && (counter==(size/4*size/4)))begin
			counter=(size/8*size/8-1);
		end
		else begin
			if(negedge_counter==5'h13)//14
				counter=counter+1;
			else
				counter=counter;
		end
end

always@(posedge clk)
begin
	if(!reset || !ready)
		Done[0]=1'b0;
	else
		if((address_counter==5'h01) && (counter==(size/8*size/8)))
			Done[0]=counter_flag;
		else
			Done[0]=1'b0;
end

always@(negedge clk)//posedge
begin
	if(!reset ||!ready || !initial_pass)begin
		initial_counter=0;
		Done[1]=1'b0;
	end
	else begin
		if(initial_counter==5'h14)begin
			initial_counter=0;
			Done[1]=1'b1;
		end
		else begin
			initial_counter=initial_counter+1'b1;
			Done[1]=1'b0;
		end
	end
end


	
always@(address_counter or counter)
begin
	//select=counter[0];
	case(address_counter)
	5'b00000:begin  z_addr=counter;						//0
			address={z_addr[17:12],z_addr[11],z_addr[9],z_addr[7],z_addr[5],z_addr[3],z_addr[1],z_addr[10],z_addr[8],z_addr[6],z_addr[4],z_addr[2],z_addr[0]};
			posedge_counter=5'h14;end
	5'b00001:begin		z_addr={counter<<2};				//1
			address={z_addr[17:14],z_addr[13],z_addr[11],z_addr[9],z_addr[7],z_addr[5],z_addr[3],z_addr[1],z_addr[12],z_addr[10],z_addr[8],z_addr[6],z_addr[4],z_addr[2],z_addr[0]};
			posedge_counter=5'h00;end
	5'b00010:begin  z_addr={counter<<2}+2'b01;						//2
			address={z_addr[17:14],z_addr[13],z_addr[11],z_addr[9],z_addr[7],z_addr[5],z_addr[3],z_addr[1],z_addr[12],z_addr[10],z_addr[8],z_addr[6],z_addr[4],z_addr[2],z_addr[0]};
			posedge_counter=5'h01;end
	5'b00011:begin  z_addr={counter<<2}+2'b10;						//3
			address={z_addr[17:14],z_addr[13],z_addr[11],z_addr[9],z_addr[7],z_addr[5],z_addr[3],z_addr[1],z_addr[12],z_addr[10],z_addr[8],z_addr[6],z_addr[4],z_addr[2],z_addr[0]};
			posedge_counter=5'h02;end
	5'b00100:begin  z_addr={counter<<2}+2'b11;						//4
			address={z_addr[17:14],z_addr[13],z_addr[11],z_addr[9],z_addr[7],z_addr[5],z_addr[3],z_addr[1],z_addr[12],z_addr[10],z_addr[8],z_addr[6],z_addr[4],z_addr[2],z_addr[0]};
			posedge_counter=5'h03;end
	5'b00101:begin  z_addr={counter<<4};						//5
			address={z_addr[17:16],z_addr[15],z_addr[13],z_addr[11],z_addr[9],z_addr[7],z_addr[5],z_addr[3],z_addr[1],z_addr[14],z_addr[12],z_addr[10],z_addr[8],z_addr[6],z_addr[4],z_addr[2],z_addr[0]};
			posedge_counter=5'h04;end
	5'b00110:begin  z_addr={counter<<4}+4'h1;						//6
			address={z_addr[17:16],z_addr[15],z_addr[13],z_addr[11],z_addr[9],z_addr[7],z_addr[5],z_addr[3],z_addr[1],z_addr[14],z_addr[12],z_addr[10],z_addr[8],z_addr[6],z_addr[4],z_addr[2],z_addr[0]};
			posedge_counter=5'h05;end
	5'b00111:begin  z_addr={counter<<4}+4'h2;						//7
			address={z_addr[17:16],z_addr[15],z_addr[13],z_addr[11],z_addr[9],z_addr[7],z_addr[5],z_addr[3],z_addr[1],z_addr[14],z_addr[12],z_addr[10],z_addr[8],z_addr[6],z_addr[4],z_addr[2],z_addr[0]};
			posedge_counter=5'h06;end
	5'b01000:begin  z_addr={counter<<4}+4'h3;						//8
			address={z_addr[17:16],z_addr[15],z_addr[13],z_addr[11],z_addr[9],z_addr[7],z_addr[5],z_addr[3],z_addr[1],z_addr[14],z_addr[12],z_addr[10],z_addr[8],z_addr[6],z_addr[4],z_addr[2],z_addr[0]};
			posedge_counter=5'h07;end
	5'b01001:begin  z_addr={counter<<4}+4'h4;						//9
			address={z_addr[17:16],z_addr[15],z_addr[13],z_addr[11],z_addr[9],z_addr[7],z_addr[5],z_addr[3],z_addr[1],z_addr[14],z_addr[12],z_addr[10],z_addr[8],z_addr[6],z_addr[4],z_addr[2],z_addr[0]};
			posedge_counter=5'h08;end
	5'b01010:begin  z_addr={counter<<4}+4'h5;						//10
			address={z_addr[17:16],z_addr[15],z_addr[13],z_addr[11],z_addr[9],z_addr[7],z_addr[5],z_addr[3],z_addr[1],z_addr[14],z_addr[12],z_addr[10],z_addr[8],z_addr[6],z_addr[4],z_addr[2],z_addr[0]};
			posedge_counter=5'h09;end
	5'b01011:begin  z_addr={counter<<4}+4'h6;						//11
			address={z_addr[17:16],z_addr[15],z_addr[13],z_addr[11],z_addr[9],z_addr[7],z_addr[5],z_addr[3],z_addr[1],z_addr[14],z_addr[12],z_addr[10],z_addr[8],z_addr[6],z_addr[4],z_addr[2],z_addr[0]};
			posedge_counter=5'h0a;end
	5'b01100:begin  z_addr={counter<<4}+4'h7;						//12
			address={z_addr[17:16],z_addr[15],z_addr[13],z_addr[11],z_addr[9],z_addr[7],z_addr[5],z_addr[3],z_addr[1],z_addr[14],z_addr[12],z_addr[10],z_addr[8],z_addr[6],z_addr[4],z_addr[2],z_addr[0]};
			posedge_counter=5'h0b;end
	5'b01101:begin  z_addr={counter<<4}+4'h8;						//13
			address={z_addr[17:16],z_addr[15],z_addr[13],z_addr[11],z_addr[9],z_addr[7],z_addr[5],z_addr[3],z_addr[1],z_addr[14],z_addr[12],z_addr[10],z_addr[8],z_addr[6],z_addr[4],z_addr[2],z_addr[0]};
			posedge_counter=5'h0c;end
	5'b01110:begin  z_addr={counter<<4}+4'h9;						//14
			address={z_addr[17:16],z_addr[15],z_addr[13],z_addr[11],z_addr[9],z_addr[7],z_addr[5],z_addr[3],z_addr[1],z_addr[14],z_addr[12],z_addr[10],z_addr[8],z_addr[6],z_addr[4],z_addr[2],z_addr[0]};
			posedge_counter=5'h0d;end
	5'b01111:begin  z_addr={counter<<4}+4'ha;						//15
			address={z_addr[17:16],z_addr[15],z_addr[13],z_addr[11],z_addr[9],z_addr[7],z_addr[5],z_addr[3],z_addr[1],z_addr[14],z_addr[12],z_addr[10],z_addr[8],z_addr[6],z_addr[4],z_addr[2],z_addr[0]};
			posedge_counter=5'h0e;end
	5'b10000:begin  z_addr={counter<<4}+4'hb;						//16
			address={z_addr[17:16],z_addr[15],z_addr[13],z_addr[11],z_addr[9],z_addr[7],z_addr[5],z_addr[3],z_addr[1],z_addr[14],z_addr[12],z_addr[10],z_addr[8],z_addr[6],z_addr[4],z_addr[2],z_addr[0]};
			posedge_counter=5'h0f;end
	5'b10001:begin  z_addr={counter<<4}+4'hc;						//17
			address={z_addr[17:16],z_addr[15],z_addr[13],z_addr[11],z_addr[9],z_addr[7],z_addr[5],z_addr[3],z_addr[1],z_addr[14],z_addr[12],z_addr[10],z_addr[8],z_addr[6],z_addr[4],z_addr[2],z_addr[0]};
			posedge_counter=5'h10;end
	5'b10010:begin  z_addr={counter<<4}+4'hd;						//18
			address={z_addr[17:16],z_addr[15],z_addr[13],z_addr[11],z_addr[9],z_addr[7],z_addr[5],z_addr[3],z_addr[1],z_addr[14],z_addr[12],z_addr[10],z_addr[8],z_addr[6],z_addr[4],z_addr[2],z_addr[0]};
			posedge_counter=5'h11;end
	5'b10011:begin  z_addr={counter<<4}+4'he;						//19
			address={z_addr[17:16],z_addr[15],z_addr[13],z_addr[11],z_addr[9],z_addr[7],z_addr[5],z_addr[3],z_addr[1],z_addr[14],z_addr[12],z_addr[10],z_addr[8],z_addr[6],z_addr[4],z_addr[2],z_addr[0]};
			posedge_counter=5'h12;end
	5'b10100:begin	 z_addr={counter<<4}+4'hf;					//20
			address={z_addr[17:16],z_addr[15],z_addr[13],z_addr[11],z_addr[9],z_addr[7],z_addr[5],z_addr[3],z_addr[1],z_addr[14],z_addr[12],z_addr[10],z_addr[8],z_addr[6],z_addr[4],z_addr[2],z_addr[0]};
			posedge_counter=5'h13;end
	default:begin	  z_addr=counter;
			address={z_addr[17:16],z_addr[15],z_addr[13],z_addr[11],z_addr[9],z_addr[7],z_addr[5],z_addr[3],z_addr[1],z_addr[14],z_addr[12],z_addr[10],z_addr[8],z_addr[6],z_addr[4],z_addr[2],z_addr[0]};
			posedge_counter=5'h01;end
	endcase
end

always@(posedge clk)//negedge
begin
	if(!reset || !ready)
		negedge_counter=0;
	else
		negedge_counter=posedge_counter;
end


endmodule


module symbol_generator(clk,reset,ready,negedge_counter,posedge_counter,address_counter,In_SMAP_data,In_SAQ_data,In_SAQ_counter,In_IZ_flag,counter_flag,counter,Set,Out_Data);

parameter	size=512;

input		clk,reset,ready;
input	[4:0]	negedge_counter,posedge_counter;
input	[17:0]	address_counter;
input	[41:0]	In_SMAP_data;
input	[20:0]	In_SAQ_data;
input	[4:0]	In_SAQ_counter,In_IZ_flag;

output		counter_flag;
output	[4:0]	counter;
output		Set;
output	[1:0]	Out_Data;


reg		sign,SAQ_flag;
reg		Set;
reg	[1:0]	Out_Data;
reg	[4:0]	counter,counter_reg;
reg		counter_flag;


always @(negedge_counter or In_SMAP_data or In_SAQ_data or In_SAQ_counter or In_IZ_flag or SAQ_flag or counter_reg or address_counter)	//In_bitplane{significant,sign,refinement,refinimint}
begin
	if(!reset || !ready )
	begin
		Set=1'b0;
		Out_Data=2'bxx;
	end
	else
	begin
		if(In_SMAP_data[({1'b0,negedge_counter}<<1'b1)+1'b1]==1'b1 && counter==5'b00000 && address_counter>(size/8*size/8))begin
			Set=1'b1;
			if(In_SMAP_data[{1'b0,negedge_counter}<<1'b1]==1'b0)
				Out_Data=2'b00;//Positive Significant
			else
				Out_Data=2'b01;//Negative	Significant
		end
		else begin
			if(negedge_counter==0 && address_counter>(size/8*size/8))begin
				Set=1'b1;
				if(In_IZ_flag[0]==1'b1)	begin
					Out_Data=2'b11;//Isolated Zero
				end	
				else begin
					Out_Data=2'b10;//Zerotree Root
				end
			end
			else begin
				if(SAQ_flag)begin
					Set=1'b1;
					Out_Data={1'b1,In_SAQ_data[counter_reg]};
				end
				else begin
					if(In_IZ_flag[0]==0)	begin
						Set=1'b0;
						Out_Data=2'bxx;
					end
					else if(negedge_counter<5) begin
						Set=1'b1;
						if(In_IZ_flag[negedge_counter]==1'b1) begin
							Out_Data=2'b11;//Isolated Zero
						end
						else begin
							Out_Data=2'b10;//Zerotree Root
						end
					end
					else if((In_IZ_flag[(negedge_counter-1'b1)>>2]) && SAQ_flag==1'b0)begin
						Set=1'b1;
						Out_Data=2'b10;//Zerotree Root
					end
					else begin
						Set=1'b0;
						Out_Data=2'bxx;
					end
				end
			end
		end
	end
end

always@(posedge clk)
begin
	if(!reset || !ready) begin
		counter_flag=1'b1;
		SAQ_flag=1'b0;
	end
	else
		if(posedge_counter==5'b10100) begin
			if(counter==In_SAQ_counter) begin
				counter_flag=1'b1;
				if(In_SAQ_counter==5'b00000)
					SAQ_flag=1'b0;
				else
					SAQ_flag=1'b1;
			end
			else begin
				counter_flag=1'b0;
				if(counter>5'b00000)
					SAQ_flag=1'b1;
				else
					SAQ_flag=1'b0;
			end
		end
		else begin
			counter_flag=1'b0;
			SAQ_flag=1'b0;
		end
end

always@(negedge clk)
begin
	if(!reset || !ready) begin
		counter=5'b00000;
		
	end
	else
		if(negedge_counter==5'h14)
			if(counter==In_SAQ_counter) begin
				counter=5'b00000;
				
			end
			else begin
				counter=counter+1'b1;
				//sign=In_SAQ_data[counter-1'b1];
			end
		else begin
			counter=5'b00000;
			
		end
end

always@(posedge clk)
begin
	if(!reset || !ready) begin
		counter_reg=5'b00000;
	end
	else begin
		counter_reg=counter-1'b1;
	end
end
endmodule