ezw_512.v

EZW Embedded Zero-tree Wavelets Encoding,video codecs from the EZW family which use a 3D version of

`timescale 1ns/10ps
module FDWT_EZW_TOP(clk,reset,Pass,EZW_in,In_Threshold,Address_R,Select,Set,Out_Data,Out_MLF);
input		clk,reset;
input	[2:0]	Pass;
input	[8:0]	EZW_in;
input	[7:0]	In_Threshold;
input	[17:0]	Address_R;

output		Select,Set;
output	[1:0]	Out_Data;
output	[8:0]	Out_MLF;


wire	[5:0]	wire_DataPath;
wire		wire_LL3_Done;
wire	[1:0]	wire_Done;
wire	[2:0]	wire_Pass;
wire		set_datapath,set_ll3;
wire	[17:0]	address_datapath,address_ll3;

Pass_reg			pass(.clk(clk),.reset(reset),.read(wire_DataPath[5]),.In_Pass(Pass),.Out_Pass(wire_Pass));

FDWT_EZW_control			Control(.clk(clk),.reset(reset),.LL3_Done(wire_LL3_Done),.Pass_Done(wire_Done),.Pass(wire_Pass),.Out_EZW_DataPath(wire_DataPath));

most_low_freq			MLF(.clk(clk),.reset(reset),.ready(wire_DataPath[4]),.EZW_in(EZW_in),.write_en(set_ll3),.EZW_out(Out_MLF),.address_R(address_ll3),.Done(wire_LL3_Done));

EZW_DataPath 			DataPath(.clk(clk),.reset(reset),.ready(wire_DataPath[2]),.EZW_in(EZW_in),.In_Threshold(In_Threshold),.T_read(wire_DataPath[5]),.division(wire_DataPath[0]),.initial_pass(wire_DataPath[3]),.start_pass(wire_DataPath[1]),.address_R(address_datapath),
				.Set(set_datapath),.Out_Data(Out_Data),.Done(wire_Done));

assign	Set=(wire_DataPath[4])?set_ll3:set_datapath;
assign	Address_R=(wire_DataPath[4])?address_ll3:address_datapath;
assign	Select=wire_DataPath[2];
endmodule


module Pass_reg(clk,reset,read,In_Pass,Out_Pass);
input		clk,reset,read;
input	[2:0]	In_Pass;

output	[2:0]	Out_Pass;

reg	[2:0]	Out_Pass;

always @(posedge clk) begin
	if(!reset)
		Out_Pass=0;
	else
		if(read)
			Out_Pass=In_Pass;
		else
			Out_Pass=Out_Pass;
end
endmodule


module most_low_freq(clk,reset,ready,EZW_in,write_en,EZW_out,address_R,Done);

parameter	size=512;

input		clk,reset,ready;
input	[8:0]	EZW_in;
output		write_en;
output	[8:0]	EZW_out;
output	[17:0]	address_R;
output		Done;

reg		Done,write_en;
reg	[17:0]	address_R,address_W;

reg	[8:0]	EZW_out;

always @(posedge clk)
begin
	if(!reset || !ready) begin
		address_R=15'h0000;
	end
	else
		if(address_R==(size/8*size/8)) begin
			address_R=16'h0000;
		end
		else begin
			address_R=address_R+1'b1;
		end
end

always@(posedge clk)
begin
	if(!reset || !ready)
		Done=1'b0;
	else
		if(address_R==(size/8*size/8))
			Done=1'b1;
		else
			Done=1'b0;
end

always@(posedge clk)
begin
	if(!reset || !ready) begin
		write_en=1'b0;
	end
	else begin
		if(address_R==16'h0001)
			write_en=1'b1;
		else if(address_R==16'h0000)
			write_en=1'b0;
		else
			write_en=write_en;
	end
end

always@(posedge clk)
begin
	if(!reset || !ready) begin
		EZW_out=9'h000;
	end
	else begin
		EZW_out=EZW_in;
	end
end
endmodule


module FDWT_EZW_control(clk,reset,LL3_Done,Pass_Done,Pass,Out_EZW_DataPath);
input		clk,reset;
input		LL3_Done;
input	[1:0]	Pass_Done;
input	[2:0]	Pass;

output	[5:0]	Out_EZW_DataPath;


parameter	S0=0;
parameter	S1=1;
parameter	S2=2;
parameter	S3=3;
parameter	S4=4;
parameter	S5=5;
parameter	S6=6;

reg	[2:0]	NextState,CurrentState;
reg	[2:0]	pass_counter;
reg	[5:0]	Out_EZW_DataPath;

always@(posedge clk or negedge reset)
begin
	if(!reset)
		CurrentState = S0;
	else
		CurrentState = NextState;
end

always@(CurrentState or reset or Pass_Done or LL3_Done)
begin
	case(CurrentState)
		S0:begin
			if(!reset)
				NextState = S0;
			else
				NextState = S1;
		end
		
		S1:begin
		//	if(read_threshold)
				NextState = S2;//S2
		//	else
		//		NextState = S1;
		end

		S2:begin
			if(LL3_Done)
				NextState = S3;
			else
				NextState = S2;
		end 

		S3:begin
			if(Pass_Done[1])
				NextState = S4;
			else
				NextState = S3;
		end
		
		S4:begin
			if(Pass_Done[0])
				NextState = S5;
			else
				NextState = S4;
		end
		
		S5:	NextState = S6;
		
		S6:begin
			if(pass_counter==Pass)
				NextState = S6;
			else
				NextState = S3;
		end
		
		default:NextState = S0;
	endcase
end

always@(CurrentState)
begin
	case(CurrentState)
		S0:	Out_EZW_DataPath=6'b0_0_0_0_0_0;//reset system
		S1:	Out_EZW_DataPath=6'b1_0_0_0_0_0;//read threshold
		S2:	Out_EZW_DataPath=6'b0_1_0_0_0_0;//put LL3
		S3:	Out_EZW_DataPath=6'b0_0_1_1_0_0;//initial EZW
		S4:	Out_EZW_DataPath=6'b0_0_0_1_1_0;//start EZW
		S5:	Out_EZW_DataPath=6'b0_0_0_0_0_1;//shift threshold
		S6:	Out_EZW_DataPath=6'b0_0_0_0_0_0;
		default:Out_EZW_DataPath=6'b0_0_0_0_0_0;
	endcase
end

always@(posedge clk or negedge reset)
begin
	if(!reset)
		pass_counter=0;
	else
		if(Pass_Done[0])
			pass_counter=pass_counter+1'b1;
		else
			pass_counter=pass_counter;
end
endmodule



module EZW_DataPath(clk,reset,ready,EZW_in,In_Threshold,T_read,division,initial_pass,start_pass,address_R,Set,Out_Data,Done);

parameter Data_Width = 8;

input				clk,reset,ready,T_read,division,initial_pass,start_pass;
input	[Data_Width:0]			EZW_in;
input	[Data_Width-1:0]			In_Threshold;

output	[17:0]			address_R;
output				Set;
output	[1:0]			Done;
output	[1:0]			Out_Data;


wire	[Data_Width-1:0]			wire_threshold;
wire	[41:0]			wire_SMAP_data_reg,wire_SMAP_data;
wire	[20:0]			wire_SAQ_data_reg,wire_SAQ_data;
wire	[4:0]			wire_SAQ_counter_reg,wire_iz_flag_reg,wire_SAQ_counter,wire_IZ_flag;
wire	[4:0]			wire_pos_counter,wire_neg_counter,wire_counter;
wire	[17:0]			wire_address_counter;
wire				Set,wire_counter_flag;
wire	[1:0]			Out_Data;


threshold_reg		threshold_reg0(.clk(clk),.reset(reset),.division(division),.read(T_read),.In_threshold(In_Threshold),.Out_threshold(wire_threshold));

bitplane		bitplane_u0(.clk(clk),.reset(reset),.ready(ready),.EZW_in(EZW_in),.threshold(wire_threshold),.posedge_counter(wire_pos_counter),.negedge_counter(wire_neg_counter),.counter(wire_counter),.SMAP_data(wire_SMAP_data_reg),.SAQ_data(wire_SAQ_data_reg),.SAQ_counter(wire_SAQ_counter_reg),.iz_flag(wire_iz_flag_reg));
bitplane_reg		bit_reg_r1(.clk(clk),.reset(reset),.ready(start_pass),.counter_flag(wire_counter_flag),.negedge_counter(wire_neg_counter),.In_SMAP_data(wire_SMAP_data_reg),.In_SAQ_data(wire_SAQ_data_reg),.In_SAQ_counter(wire_SAQ_counter_reg),.In_IZ_flag(wire_iz_flag_reg),.Out_SMAP_data(wire_SMAP_data),.Out_SAQ_data(wire_SAQ_data),.Out_SAQ_counter(wire_SAQ_counter),.Out_IZ_flag(wire_IZ_flag));

address_generator	 address_u1(.clk(clk),.reset(reset),.ready(ready),.initial_pass(initial_pass),.counter_flag(wire_counter_flag),.address(address_R),.posedge_counter(wire_pos_counter),.negedge_counter(wire_neg_counter),.counter(wire_address_counter),.Done(Done));

symbol_generator symbol_u1(.clk(clk),.reset(reset),.ready(start_pass),.posedge_counter(wire_pos_counter),.negedge_counter(wire_neg_counter),.address_counter(wire_address_counter),.In_SMAP_data(wire_SMAP_data),.In_SAQ_data(wire_SAQ_data),.In_SAQ_counter(wire_SAQ_counter),.In_IZ_flag(wire_IZ_flag),.counter_flag(wire_counter_flag),.counter(wire_counter),.Set(Set),.Out_Data(Out_Data));

endmodule


module threshold_reg(clk,reset,division,read,In_threshold,Out_threshold);
input		clk,reset,division,read;
input	[7:0]	In_threshold;

output	[7:0]	Out_threshold;

reg	[7:0]	Out_threshold;

always @(posedge clk) begin
	if(!reset)
		Out_threshold=0;
	else
		if(read)
			Out_threshold=In_threshold;
		else
			if(division)
				Out_threshold=Out_threshold >> 1;
			else
				Out_threshold=Out_threshold;
end
endmodule


module bitplane(clk,reset,ready,EZW_in,threshold,posedge_counter,negedge_counter,counter,SMAP_data,SAQ_data,SAQ_counter,iz_flag);

parameter Data_Width = 8;

input				clk,reset,ready;
input	[Data_Width:0]			EZW_in;
input	[Data_Width-1:0]threshold;
input	[4:0]			posedge_counter,negedge_counter,counter;

output	[41:0]			SMAP_data;
output	[20:0]			SAQ_data;
output	[4:0]			SAQ_counter;
output	[4:0]			iz_flag;

reg	[1:0]			data;
reg	[20:0]			SAQ_data;
reg	[41:0]			SMAP_data;
reg	[4:0]			SAQ_counter;
reg	[4:0]			iz_flag,reg_flag;


//------------------------------------SMAP------------------------------------
always @(EZW_in or threshold) 
begin
	if(EZW_in[7:0] >= threshold[7:0])begin
		if({1'b0,EZW_in[7:0]} >= ({1'b0,threshold[7:0]}<<1))begin
			data={1'b0,1'b0};
		end
		else begin
			data={1'b1,EZW_in[8]};
		end
	end
	else begin
		data=2'b00;
	end
end


always @(posedge clk)//negedge
begin
	if(!reset || !ready)
		SMAP_data=0;
	else
		if(posedge_counter==5'h00)
			SMAP_data={42'h0000000000,data};
		else
			if(counter==5'b00000)
				{SMAP_data[(({1'b0,posedge_counter}<<1'b1)+1'b1)],SMAP_data[{1'b0,posedge_counter}<<1'b1]}=data;//+1
			else
				SMAP_data=SMAP_data;
end

//----------------------------------SAQ-------------------------------
always@(posedge clk)
begin
	if(!reset || !ready) begin
		SAQ_data=21'h000000;
		SAQ_counter=5'b00000;
	end
	else begin
		if(posedge_counter==5'b00000) begin	
			if(EZW_in[7:0] >= threshold[7:0])begin
				SAQ_data={20'h00000,(|(EZW_in[7:0] & (threshold[7:0]>>1)))};
				SAQ_counter=5'b00001;
			end
			else begin
				SAQ_data=21'h000000;
				SAQ_counter=5'b00000;
			end
		end
		else begin
			if((EZW_in[7:0] >= threshold[7:0]) && counter==5'b00000) begin
				SAQ_data[SAQ_counter]=(|(EZW_in[7:0] & (threshold[7:0]>>1)));
				SAQ_counter=SAQ_counter+1'b1;
			end
			else begin
				SAQ_data=SAQ_data;
				SAQ_counter=SAQ_counter;
			end
		end
	end
end

//----------------------------IZ-----------------------------
always @(EZW_in or threshold or posedge_counter or reset or ready)
begin
	if(!reset || !ready)
		reg_flag=5'b00000;
	else if(({1'b0,EZW_in[7:0]} < ({1'b0,threshold[7:0]}<<1)) && (|(EZW_in[7:0] & threshold[7:0])))begin
		case(posedge_counter)
		5'b00000:reg_flag=5'b00001;
		5'b00001:reg_flag=5'b00011;
		5'b00010:reg_flag=5'b00101;
		5'b00011:reg_flag=5'b01001;
		5'b00100:reg_flag=5'b10001;
		
		5'b00101:reg_flag=5'b00011;
		5'b00110:reg_flag=5'b00011;
		5'b00111:reg_flag=5'b00011;
		5'b01000:reg_flag=5'b00011;
		
		5'b01001:reg_flag=5'b00101;
		5'b01010:reg_flag=5'b00101;
		5'b01011:reg_flag=5'b00101;