mcu.h

用AT89C5131A开发USB的框架很好用

Sbit  (TXD,       P3,      1);
Sbit  (RXD,       P3,      0);

Sbit  (P4_7,      P4,      7);
Sbit  (P4_6,      P4,      6);
Sbit  (P4_5,      P4,      5);
Sbit  (P4_4,      P4,      4);
Sbit  (P4_3,      P4,      3);
Sbit  (P4_2,      P4,      2);
Sbit  (P4_1,      P4,      1);
Sbit  (P4_0,      P4,      0);

Sbit  (P5_3,      P5,      3);
Sbit  (P5_2,      P5,      2);
Sbit  (P5_1,      P5,      1);
Sbit  (P5_0,      P5,      0);


// POWER & SYSTEM MANAGEMENT
// Page 0
Sfr   (PSTA,      0x86);
Sfr   (PCON,      0x87);
Sfr   (AUXR1,     0xA2);
Sfr   (VBAT,      0x85);


// CLOCK MANAGEMENT
// Page 0
Sfr   (CKCON,     0x8F);
Sfr   (CKEN,      0xB9);
Sfr   (DFCCLK,    0xBA);
Sfr   (NFCCLK,    0xBC);
Sfr   (MMCCLK,    0xBD);


// INTERRUPT
// Page 0
Sfr   (IEN0,      0xA8);   // Bit addressable
Sfr   (IEN1,      0xB1);
Sfr   (IPH0,      0xB7);
Sfr   (IPH1,      0xB3);
Sfr   (IPL0,      0xB8);
Sfr   (IPL1,      0xB2);

Sbit  (EA,        IEN0,    7);
Sbit  (EAUP,      IEN0,    6);
Sbit  (EDFC,      IEN0,    5);
Sbit  (ES,        IEN0,    4);
Sbit  (ET1,       IEN0,    3);
Sbit  (EX1,       IEN0,    2);
Sbit  (ET0,       IEN0,    1);
Sbit  (EX0,       IEN0,    0);


// TIMERS
// Page 0
Sfr   (TCON,      0x88);   // Bit addressable
Sfr   (TMOD,      0x89);
Sfr   (TL0,       0x8A);
Sfr   (TL1,       0x8B);
Sfr   (TH0,       0x8C);
Sfr   (TH1,       0x8D);

Sbit  (TF1,       TCON,    7);
Sbit  (TR1,       TCON,    6);
Sbit  (TF0,       TCON,    5);
Sbit  (TR0,       TCON,    4);
Sbit  (IE1,       TCON,    3);
Sbit  (IT1,       TCON,    2);
Sbit  (IE0,       TCON,    1);
Sbit  (IT0,       TCON,    0);


// WATCHDOG
// Page 0
Sfr   (WDTRST,    0xA6);
Sfr   (WDTPRG,    0xA7);


// RAM INTERFACE
// Page 1
Sfr   (RDFCAL,    0xFD);
Sfr   (RDFCAM,    0xFE);
Sfr   (RDFCAH,    0xFF);


// MEMORY MANAGEMENT
// Page 0
Sfr   (MEMCON,    0xF1);
Sfr   (MEMCBAX,   0xF2);
Sfr   (MEMDBAX,   0xF3);
Sfr   (MEMXBAX,   0xF4);
Sfr   (MEMCSX,    0xF5);
Sfr   (MEMXSX,    0xF6);


// CONTEXT MANAGEMENT
// Page 0
Sfr   (PPCONX,    0xF7);
Sfr   (HCACCX,    0xE8);
Sfr   (HCSPX,     0xE9);
Sfr   (HCDPHX,    0xEA);
Sfr   (HCDPLX,    0xEB);
Sfr   (HCBX,      0xEC);
Sfr   (HCPSWX,    0xED);
Sfr   (HCPCHX,    0xEE);
Sfr   (HCPCLX,    0xEF);


// SCHEDULER MANAGEMENT
// Page 0
Sfr   (SCHCON,    0xFD);
Sfr   (SCHCLK,    0xFE);
Sfr   (SCHCFG,    0xFF);
// All Pages
Sfr   (SCHGPR3,   0xF9);
Sfr   (SCHGPR2,   0xFA);
Sfr   (SCHGPR1,   0xFB);
Sfr   (SCHGPR0,   0xFC);


// DATA FLOW CONTROLLER
// Page 1
Sfr   (DFCON,     0x89);
Sfr   (DFCCS,     0x88);   // Bit addressable
Sfr   (DFD0,      0x8A);
Sfr   (DFD1,      0x8B);
Sfr   (DFCRC,     0x8C);

Sbit  (DFABT1,    DFCCS,   7);
Sbit  (DFEOFE1,   DFCCS,   6);
Sbit  (DFEOFI1,   DFCCS,   5);
Sbit  (DFBSY1,    DFCCS,   4);
Sbit  (DFABT0,    DFCCS,   3);
Sbit  (DFEOFE0,   DFCCS,   2);
Sbit  (DFEOFI0,   DFCCS,   1);
Sbit  (DFBSY0,    DFCCS,   0);


// USB CONTROLLER
// USB General
// Page 1
Sfr   (USBCON,    0xE1);
Sfr   (USBSTA,    0xE2);
Sfr   (USBINT,    0xE3);
Sfr   (UDPADDH,   0xE4);
Sfr   (UDPADDL,   0xE5);
Sfr   (OTGCON,    0xE6);
Sfr   (OTGIEN,    0xE7);
Sfr   (OTGINT,    0xD1);

// USB Device
// Page 1
Sfr   (UDCON,     0xD9);
Sfr   (UDINT,     0xD8);   // bit addressable
Sfr   (UDIEN,     0xDA);
Sfr   (UDADDR,    0xDB);
Sfr   (UDFNUMH,   0xDC);
Sfr   (UDFNUML,   0xDD);
Sfr   (UDMFN,     0xDE);
Sfr   (UDTST,     0xDF);

Sbit  (UPRSMI,    UDINT,   6);
Sbit  (EORSMI,    UDINT,   5);
Sbit  (WAKEUPI,   UDINT,   4);
Sbit  (EORSTI,    UDINT,   3);
Sbit  (SOFI,      UDINT,   2);
Sbit  (MSOFI,     UDINT,   1);
Sbit  (SUSPI,     UDINT,   0);

// USB Endpoint
// Page 1
Sfr   (UENUM,     0xC9);
Sfr   (UERST,     0xCA);
Sfr   (UECONX,    0xCB);
Sfr   (UECFG0X,   0xCC);
Sfr   (UECFG1X,   0xCD);
Sfr   (UESTA0X,   0xCE);
Sfr   (UESTA1X,   0xCF);
Sfr   (UEINTX,    0xC8);   // bit addressable
Sfr   (UEIENX,    0xD2);
Sfr   (UEDATX,    0xD3);
Sfr   (UEBCHX,    0xD4);
Sfr   (UEBCLX,    0xD5);
Sfr   (UEINT,     0xD6);

Sbit  (FIFOCON,   UEINTX,  7);
Sbit  (NAKINI,    UEINTX,  6);
Sbit  (RWAL,      UEINTX,  5);
Sbit  (NAKOUTI,   UEINTX,  4);
Sbit  (RXSTPI,    UEINTX,  3);
Sbit  (RXOUTI,    UEINTX,  2);
Sbit  (STALLEDI,  UEINTX,  1);
Sbit  (TXINI,     UEINTX,  0);

// USB Host
// Page 1
Sfr   (UHCON,     0xD9);
Sfr   (UHINT,     0xD8);   // bit addressable
Sfr   (UHIEN,     0xDA);
Sfr   (UHADDR,    0xDB);
Sfr   (UHFNUMH,   0xDC);
Sfr   (UHFNUML,   0xDD);
Sfr   (UHFLEN,    0xDE);

Sbit  (HWUPI,     UHINT,   6);
Sbit  (HSOFI,     UHINT,   5);
Sbit  (RXRSMI,    UHINT,   4);
Sbit  (RSMEDI,    UHINT,   3);
Sbit  (RSTI,      UHINT,   2);
Sbit  (DDISCI,    UHINT,   1);
Sbit  (DCONNI,    UHINT,   0);

// USB Pipe
// Page 1
Sfr   (UPNUM,     0xC9);
Sfr   (UPRST,     0xCA);
Sfr   (UPCONX,    0xCB);
Sfr   (UPCFG0X,   0xCC);
Sfr   (UPCFG1X,   0xCD);
Sfr   (UPCFG2X,   0xCF);
Sfr   (UPSTAX,    0xCE);
Sfr   (UPINRQX,   0xDF);
Sfr   (UPERRX,    0xD7);
Sfr   (UPINTX,    0xC8);   // bit addressable
Sfr   (UPIENX,    0xD2);
Sfr   (UPDATX,    0xD3);
Sfr   (UPBCHX,    0xD4);
Sfr   (UPBCLX,    0xD5);
Sfr   (UPINT,     0xD6);

// Sbit  (FIFOCON,   UPINTX,  7);  // Already defined for the device
Sbit  (NAKEDI,    UPINTX,  6);
// Sbit  (RWAL,      UPINTX,  5);  // Already defined for the device
Sbit  (PERRE,     UPINTX,  4);
Sbit  (TXSTPI,    UPINTX,  3);
Sbit  (TXOUTI,    UPINTX,  2);
Sbit  (RXSTALLI,  UPINTX, 1);


// NAND FLASH CONTROLLER
// Page 1
Sfr   (NFCFG,     0x99);
Sfr   (NFLOG,     0x9A);
Sfr   (NFCON,     0x9B);
Sfr   (NFERR,     0x9C);
Sfr   (NFADR,     0x9D);
Sfr   (NFADC,     0x9E);
Sfr   (NFCMD,     0x9F);
Sfr   (NFACT,     0xA1);
Sfr   (NFDAT,     0xA2);
Sfr   (NFDATF,    0xA3);
Sfr   (NFSTA,     0x98);   // Bit addressable
Sfr   (NFECC,     0xA4);
Sfr   (NFINT,     0xA5);
Sfr   (NFIEN,     0xA6);
Sfr   (NFUDAT,    0xA7);

Sbit  (NFC_SMCD,  NFSTA,   7);
Sbit  (NFC_SMLCK, NFSTA,   6);
Sbit  (NFC_SF,    NFSTA,   5);
Sbit  (NFC_RUN,   NFSTA,   0);


// MMC CONTROLLER
// Page 1
Sfr   (MMCON0,    0xB1);
Sfr   (MMCON1,    0xB2);
Sfr   (MMCON2,    0xB3);
Sfr   (MMSTA,     0xB5);
Sfr   (MMDAT,     0xB6);
Sfr   (MMCMD,     0xB7);
Sfr   (MMINT,     0xBE);
Sfr   (MMMSK,     0xBF);


// AUDIO CONTROLLER
// Page 1
Sfr   (AUCON,     0xF1);
Sfr   (APCON0,    0xF2);
Sfr   (APCON1,    0xF3);
Sfr   (APSTA,     0xEA);
Sfr   (APDAT,     0xEB);
Sfr   (APINT,     0xF4);
Sfr   (APIEN,     0xE9);
// Page 2
Sfr   (APTIM0,    0xC6);
Sfr   (APTIM1,    0xC7);
Sfr   (APTIM2,    0xC9);
Sfr   (APRDVOL,   0xF1);
Sfr   (APLDVOL,   0xF2);
Sfr   (APBDVOL,   0xF3);
Sfr   (APMDVOL,   0xF4);
Sfr   (APTDVOL,   0xF5);
Sfr   (ACCON,     0xEA);
Sfr   (ACORG,     0xEB);
Sfr   (ACOLG,     0xEC);
Sfr   (ACIPG,     0xED);
Sfr   (ADICON0,   0xEE);
Sfr   (ADICON1,   0xEF);
Sfr   (ASCON,     0xE1);
Sfr   (ASSTA0,    0xE2);
Sfr   (ASSTA1,    0xE3);
Sfr   (ASSTA2,    0xE9);


// SPI CONTROLLER
// Page 1
Sfr   (SPCON,     0xC3);
Sfr   (SPSTA,     0xC4);
Sfr   (SPDAT,     0xC5);


// UART
// Page 1
Sfr   (SCON,      0xA8);   // Bit addressable
Sfr   (SBUF,      0xA9);

// Page 0
Sfr   (BRL,       0x91);
Sfr   (BDRCON,    0x92);

Sbit  (SM0,       SCON,    7);
Sbit  (FE,        SCON,    7);
Sbit  (SM1,       SCON,    6);
Sbit  (SM2,       SCON,    5);
Sbit  (REN,       SCON,    4);
Sbit  (TB8,       SCON,    3);
Sbit  (RB8,       SCON,    2);
Sbit  (TI,        SCON,    1);
Sbit  (RI,        SCON,    0);

// LCD INTERFACE
// Page 1
Sfr   (LCDCON0,   0x96);
Sfr   (LCDCON1,   0x8E);
Sfr   (LCDSTA,    0x8F);
Sfr   (LCDDAT,    0x97);
Sfr   (LCDBUM,    0x8D);

// KEYBOARD INTERFACE
// Page 0
Sfr   (KBCON,     0xA3);
Sfr   (KBSTA,     0xA4);

// ON CHIP DEBUG
// Page 3
Sfr   (OCDPIN,    0x89);
Sfr   (OACTIV,    0x99);
Sfr   (OBRL,      0x91);
// All Pages
Sfr   (OSCON,     0xF8);
Sfr   (OSBUF,     0x84);

*/
#endif // _MCU_H_