📄 cochlear.c
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/*******************************************************************/
/* */
/* DESCRIPTION: Cochlear Implant DSP Program */
/* */
/* AUTHOR: Liu Lixin */
/* */
/* DEVELOPMENT ENVIRONMENT: CCS2.2 FOR C5000 */
/* */
/* HISTORY: V1.0 */
/* */
/*******************************************************************/
#include <csl.h>
#include <csl_chip.h>
#include <csl_gpio.h>
#include <csl_pll.h>
#include <csl_emif.h>
#include <csl_irq.h>
#include <csl_timer.h>
#include <csl_i2c.h>
#include <csl_mcbsp.h>
#include <csl_dma.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
//#include "msp.h"
#define I2C_Addr 0x1a // I2C Slave Address of WM8950
#define AMOUNT_DATA_FRAME 80 // Amount of Sample Data per 10ms(Sampling Rate: 8KHz)
#define TIME_800ns 145 // Count Value When Timer Count down 0.8us
#define TIME_67400ns 12100 // Count Value When Timer Count down 67.4us
#define AMOUNT_CODE_BITS 24 // A Pulse Code consist of 24 bits
#define AMOUNT_ELECTRODE 16 // Amount of Electrodes
#define PULSE_WIDTH 12 // Pulse Width
#define START_BIT 0x800000 // START Bit =1;
#define N 15 //通道数
#define l1 7
#define l2 7
/*=================================================================*/
extern void delay(); // Delay
extern void init_WM8950(); // Initialize WM8950
extern void VECSTART(void); // Interrupt Vectors Table
interrupt void Power_Switch_Isr(void); // Interrupt INT0: Power_Switch_Isr
interrupt void Signal_Alter_Isr(void); // Interrupt INT1: Signal_Alter_Isr
interrupt void Alert_Bat_Isr(void); // Interrupt INT2: Alert_Bat_Isr
interrupt void Timer0_Isr(void); // Interrupt T0
interrupt void Timer1_Isr(void); // Interrupt T1
interrupt void DMA_rcv_Isr(void); // Interrupt DMA Channel0 Receiver
/*==============================================================*/
TIMER_Handle mhTimer0; // Create a TIMER_Handle object for use with TIMER_open
TIMER_Handle mhTimer1; // Create a TIMER_Handle object for use with TIMER_open
MCBSP_Handle mhMcbsp; // Create a MCBSP_Handle object for use with MCBSP_open
DMA_Handle mhDmaRcv; // Create a DMA_Handle object for use with DMA_open
/*==============================================================*/
#pragma DATA_SECTION(AUDIO_DATA0,"dmaMem")
#pragma DATA_SECTION(AUDIO_DATA1,"dmaMem")
#pragma DATA_SECTION(AUDIO_DATA2,"dmaMem")
#pragma DATA_SECTION(AUDIO_DATA3,"dmaMem")
volatile Uint16 AUDIO_DATA_SECTION; // DMA is Saving Audio Data in AUDIO_DATA0 or AUDIO_DATA1 currently:
// 0--AUDIO_DATA0;1--AUDIO_DATA1
Uint16 SIGNAL_SELECT = 0; // Select a Input Signal form Microphone or Line In:
// 0--Microphone;1--Line In
Uint16 pulse_code_bit_counter; // Pulse Code Bit Which is being sent currently
Uint16 pulse_counter; // Pulse Data Which is being sent currently
Uint16 timer_count0; // Timer0 interrupt count
Uint16 timer_count1; // Timer1 interrupt count
int AUDIO_DATA0[AMOUNT_DATA_FRAME]; // Audio Sample Data Section 0(80/10ms,8KHz/s Sampling rate)
int AUDIO_DATA1[AMOUNT_DATA_FRAME]; // Audio Sample Data Section 1(80/10ms,8KHz/s Sampling rate)
int AUDIO_DATA2[AMOUNT_DATA_FRAME]; // Audio Sample Data Section 2(80/10ms,8KHz/s Sampling rate)
int AUDIO_DATA3[AMOUNT_DATA_FRAME]; // Audio Sample Data Section 3(80/10ms,8KHz/s Sampling rate)
Uint16 Timer0_eventId; // Timer0 Interrupt EventID
Uint16 Timer1_eventId; // Timer1 Interrupt EventID
Uint16 DMA_rcvEventId; // DMA Channel 0 Interrupt EventID
long *p_pulse; // Pulse Data Pointer Which point to Pulse Data that is being sent currently;
long PULSE_DATA0[AMOUNT_DATA_FRAME]; // Pulse Data Section 0
long PULSE_DATA1[AMOUNT_DATA_FRAME]; // Pulse Data Section 1
/*=================================================================*/
/* Create a PLL Configuration structure */
PLL_Config ConfigPLL = {
1, // IAI: the PLL locks using the same process that was underway
// before the idle mode was entered
1, // IOB: If the PLL indicates a break in the phase lock,
// it switches to its bypass mode and restarts the PLL phase-locking sequence
15, // PLL multiply value; multiply 15 times
0 // Divide by 1 PLL divide value; it can be either PLL divide value
// (when PLL is enabled), or Bypass-mode divide value
// (PLL in bypass mode, if PLL multiply value is set to 1)
};
/* Create a EMIF Configuration structure */
EMIF_Config ConfigSDRAM = {
0x20, // egcr: memfreq=000b; WPE=0; MEMCEN=1; ARDYOFF=1; ARDY=0
0xFFFF, // emirst
0x3FFF, // ce01: MTYPE=011b-SDRAM
0xFFFF, // ce02: invalid
0x00FF, // ce03: invalid
0x7FFF, // ce11: MTYPE=011b-SDRAM
0xFFFF, // ce12: invalid
0x00FF, // ce13: invalid
0x7FFF, // ce21: MTYPE=011b-SDRAM
0xFFFF, // ce22: invalid
0x00FF, // ce23: invalid
0x7FFF, // ce31: MTYPE=011b-SDRAM
0xFFFF, // ce32: invalid
0x00FF, // ce33: invalid
0x4111, // sdc1: TRC=8; SDSIZE=00; RFEN=1; TRCD=2; TRP=2
0x0FFF, // sdper: 4095 Cycle
0x07FF, // init
0x0181 // sdc2: TMRD=2; TRAS=8; TACTV2ACTV=1
};
/* Create a I2C Configuration structure */
I2C_Setup Init_I2C = {
0, // 7 bit address mode
0x0000, // own address - don't care if master
184, // clkout value (Mhz)
200, // a number between 10 and 400
0, // number of bits/byte to be received or transmitted (8)
0, // DLB mode on
1 // FREE mode of operation on
};
/*
I2C_Config Config_I2C = {
0x0000, // I2COAR
0x0000, // I2CIER
0xffff, // I2CSTR
25, // I2CCLKL
25, // I2CCLKH
1, // I2CCNT
0xfffa, // I2CSAR
0x4600, // I2CMDR
0xffff, // I2CSRC
0x000b // I2CPSC
};*/
/* Create TIMER0 configuration structure */
TIMER_Config timCfg0 = {
TIMER_TCR_RMK(
TIMER_TCR_IDLEEN_DEFAULT, // IDLEEN == 0
TIMER_TCR_FUNC_OF(0), // FUNC == 0
TIMER_TCR_TLB_RESET, // TLB == 1
TIMER_TCR_SOFT_BRKPTNOW, // SOFT == 0
TIMER_TCR_FREE_WITHSOFT, // FREE == 0
TIMER_TCR_PWID_OF(0), // PWID == 0
TIMER_TCR_ARB_RESET, // ARB == 1
TIMER_TCR_TSS_START, // TSS == 0
TIMER_TCR_CP_PULSE, // CP == 0
TIMER_TCR_POLAR_LOW, // POLAR == 0
TIMER_TCR_DATOUT_0 // DATOUT == 0
), // TCR0
TIME_800ns, // PRD0
0x0000 // PRSC0
};
/* Create TIMER1 configuration structure */
TIMER_Config timCfg1 = {
TIMER_TCR_RMK(
TIMER_TCR_IDLEEN_DEFAULT, // IDLEEN == 0
TIMER_TCR_FUNC_OF(0), // FUNC == 0
TIMER_TCR_TLB_RESET, // TLB == 1
TIMER_TCR_SOFT_BRKPTNOW, // SOFT == 0
TIMER_TCR_FREE_WITHSOFT, // FREE == 0
TIMER_TCR_PWID_OF(0), // PWID == 0
TIMER_TCR_ARB_RESET, // ARB == 1
TIMER_TCR_TSS_STOP, // TSS == 0
TIMER_TCR_CP_PULSE, // CP == 0
TIMER_TCR_POLAR_LOW, // POLAR == 0
TIMER_TCR_DATOUT_0 // DATOUT == 0
), // TCR1
TIME_67400ns, // PRD1
0x0000 // PRSC1
};
/* Create a MCBSP configuration structure */
MCBSP_Config Config_MCBSP = {
MCBSP_SPCR1_RMK(
MCBSP_SPCR1_DLB_OFF, // DLB = 0
MCBSP_SPCR1_RJUST_RZF, // RJUST = 01
MCBSP_SPCR1_CLKSTP_DISABLE, // CLKSTP = 00
MCBSP_SPCR1_DXENA_ON, // DXENA = 1
MCBSP_SPCR1_ABIS_DISABLE, // ABIS = 0
MCBSP_SPCR1_RINTM_RRDY, // RINTM = 0
0, // RSYNCER = 0
0, // RFULL = 0 N/A
0, // RRDY = 0 N/A
MCBSP_SPCR1_RRST_DISABLE // RRST = 0
),
MCBSP_SPCR2_RMK(
MCBSP_SPCR2_FREE_NO, // FREE = 0
MCBSP_SPCR2_SOFT_NO, // SOFT = 0
MCBSP_SPCR2_FRST_FSG, // FRST = 0
MCBSP_SPCR2_GRST_CLKG, // GRST = 0
MCBSP_SPCR2_XINTM_XRDY, // XINTM = 0
0, // XSYNCER = N/A
0, // XEMPTY = N/A
0, // XRDY = N/A
MCBSP_SPCR2_XRST_DISABLE // XRST = 0
),
MCBSP_RCR1_RMK(
MCBSP_RCR1_RFRLEN1_OF(0), // RFRLEN1 = 0 - 1 Word
MCBSP_RCR1_RWDLEN1_16BIT // RWDLEN1 = 2
),
MCBSP_RCR2_RMK(
MCBSP_RCR2_RPHASE_SINGLE, // RPHASE = 0
MCBSP_RCR2_RFRLEN2_OF(0), // RFRLEN2 = 0
MCBSP_RCR2_RWDLEN2_8BIT, // RWDLEN2 = 0
MCBSP_RCR2_RCOMPAND_MSB, // RCOMPAND = 0
MCBSP_RCR2_RFIG_YES, // RFIG = 0
MCBSP_RCR2_RDATDLY_1BIT // RDATDLY = 1
),
MCBSP_XCR1_RMK(
MCBSP_XCR1_XFRLEN1_OF(0), // XFRLEN1 = 1
MCBSP_XCR1_XWDLEN1_16BIT // XWDLEN1 = 2
),
MCBSP_XCR2_RMK(
MCBSP_XCR2_XPHASE_SINGLE, // XPHASE = 0
MCBSP_XCR2_XFRLEN2_OF(0), // XFRLEN2 = 0
MCBSP_XCR2_XWDLEN2_8BIT, // XWDLEN2 = 0
MCBSP_XCR2_XCOMPAND_MSB, // XCOMPAND = 0
MCBSP_XCR2_XFIG_YES, // XFIG = 0
MCBSP_XCR2_XDATDLY_1BIT // XDATDLY = 1
),
MCBSP_SRGR1_DEFAULT,
MCBSP_SRGR2_DEFAULT,
MCBSP_MCR1_DEFAULT,
MCBSP_MCR2_DEFAULT,
MCBSP_PCR_RMK(
MCBSP_PCR_IDLEEN_RESET, // IDLEEN = 0
MCBSP_PCR_XIOEN_SP, // XIOEN = 0
MCBSP_PCR_RIOEN_SP, // RIOEN = 0
MCBSP_PCR_FSXM_EXTERNAL, // FSXM = 0
MCBSP_PCR_FSRM_EXTERNAL, // FSRM = 0
MCBSP_PCR_CLKXM_INPUT, // CLKXM = 0
MCBSP_PCR_CLKRM_INPUT, // CLKRM = 0
MCBSP_PCR_SCLKME_NO, // SCLKME = 0
0, // CLKSSTAT = N/A
0, // DXSTAT = N/A
0, // DRSTAT = N/
MCBSP_PCR_FSXP_ACTIVEHIGH, // FSXP = 0
MCBSP_PCR_FSRP_ACTIVELOW, // FSRP = 1
MCBSP_PCR_CLKXP_FALLING, // CLKXP = 1
MCBSP_PCR_CLKRP_RISING // CLKRP = 1
),
MCBSP_RCERA_DEFAULT,
MCBSP_RCERB_DEFAULT,
MCBSP_RCERC_DEFAULT,
MCBSP_RCERD_DEFAULT,
MCBSP_RCERE_DEFAULT,
MCBSP_RCERF_DEFAULT,
MCBSP_RCERG_DEFAULT,
MCBSP_RCERH_DEFAULT,
MCBSP_XCERA_DEFAULT,
MCBSP_XCERB_DEFAULT,
MCBSP_XCERC_DEFAULT,
MCBSP_XCERD_DEFAULT,
MCBSP_XCERE_DEFAULT,
MCBSP_XCERF_DEFAULT,
MCBSP_XCERG_DEFAULT,
MCBSP_XCERH_DEFAULT
};
/* Create DMA Receive Side Configuration */
DMA_Config DMAConfig_Rcv = { // DMACSDP
DMA_DMACSDP_RMK(
DMA_DMACSDP_DSTBEN_NOBURST, // dstben = 0
DMA_DMACSDP_DSTPACK_OFF, // dstpack = 0
DMA_DMACSDP_DST_DARAM, // dst = 0
DMA_DMACSDP_SRCBEN_NOBURST, // srcben = 0
DMA_DMACSDP_SRCPACK_OFF, // srcpack = 0
DMA_DMACSDP_SRC_PERIPH, // src = 3
DMA_DMACSDP_DATATYPE_16BIT // datatype = 1
),
DMA_DMACCR_RMK( // DMACCR
DMA_DMACCR_DSTAMODE_POSTINC, // dstamode = 1
DMA_DMACCR_SRCAMODE_CONST, // srcamode = 0
DMA_DMACCR_ENDPROG_OFF, // endprog = 0
DMA_DMACCR_REPEAT_OFF, // repeat = 0
DMA_DMACCR_AUTOINIT_ON, // autoinit = 1
DMA_DMACCR_EN_STOP, // en = 0
DMA_DMACCR_PRIO_LOW, // prio = 0
DMA_DMACCR_FS_DISABLE, // fs = 0
DMA_DMACCR_SYNC_REVT1 // sync = 0
),
DMA_DMACICR_RMK( // DMACICR
DMA_DMACICR_BLOCKIE_OFF, // blockie = 0
DMA_DMACICR_LASTIE_OFF, // lastie = 0
DMA_DMACICR_FRAMEIE_ON, // frameie = 1
DMA_DMACICR_FIRSTHALFIE_OFF, // firsthalfie = 0
DMA_DMACICR_DROPIE_OFF, // dropie = 0
DMA_DMACICR_TIMEOUTIE_OFF // timeoutie = 0
),
(DMA_AdrPtr)(MCBSP_ADDR(DRR11)), // DMACSSAL
0, // DMACSSAU
(DMA_AdrPtr)&AUDIO_DATA0, // DMACDSAL
0, // DMACDSAU
AMOUNT_DATA_FRAME, // DMACEN
1, // DMACFN
0, // DMACSFI
0, // DMACSEI
0, // DMACDFI
0 // DMACDFI
};
/*==============================================================*/
main()
{
Uint16 i;
Uint16 srcAddrHi, srcAddrLo;
Uint16 dstAddrHi, dstAddrLo;
Uint16 process_data0_mark;
Uint16 process_data1_mark;
Uint16 process_data2_mark;
Uint16 process_data3_mark;
int *p1;
long temp0,temp1;
long electrode_select; // Electrode Select
long pulse_width; // Pulse Width
long *p_code; // Point to Pulse Data for Coding
/* Initialize CSL Library */
CSL_init();
/* Set I/O Direction */
GPIO_RSET(IODIR,0xFF);
GPIO_RSET(IODATA,0x3F); // Light Green LED,Pulse Data Line is Low
/* Initialize DSP Clock */
CHIP_RSET(XBSR,0x8001); // Disable CLKOUT,Full EMIF mode, McBSP1 Mode, McBSP2 Mode
PLL_config(&ConfigPLL); // Set CPU Clock = 15/1 clkin = 184.32MHz
/* Initialize I2C */
I2C_setup(&Init_I2C);
init_WM8950(); // Initialize WM8950
/* Initialize SDRAM */
EMIF_config(&ConfigSDRAM); // Config SDRAM
AUDIO_DATA_SECTION = 0;
for(i=0;i<AMOUNT_DATA_FRAME;i++)
{
PULSE_DATA0[i] = 0;
PULSE_DATA1[i] = 0;
}
delay();
/* change the word address to a byte address for the DMA transfer */
srcAddrHi = (Uint16)(((Uint32)(DMAConfig_Rcv.dmacssal)) >> 15) & 0xFFFFu;
srcAddrLo = (Uint16)(((Uint32)(DMAConfig_Rcv.dmacssal)) << 1) & 0xFFFFu;
dstAddrHi = (Uint16)(((Uint32)(DMAConfig_Rcv.dmacdsal)) >> 15) & 0xFFFFu;
dstAddrLo = (Uint16)(((Uint32)(DMAConfig_Rcv.dmacdsal)) << 1) & 0xFFFFu;
DMAConfig_Rcv.dmacssal = (DMA_AdrPtr)srcAddrLo;
DMAConfig_Rcv.dmacssau = srcAddrHi;
DMAConfig_Rcv.dmacdsal = (DMA_AdrPtr)dstAddrLo;
DMAConfig_Rcv.dmacdsau = dstAddrHi;
IRQ_setVecs((Uint32)(&VECSTART)); // Set IVPH/IVPD to start of interrupt vector table
mhTimer0 = TIMER_open(TIMER_DEV0, TIMER_OPEN_RESET); // Open Timer0, set registers to power on defaults
mhTimer1 = TIMER_open(TIMER_DEV1, TIMER_OPEN_RESET); // Open Timer1, set registers to power on defaults
Timer0_eventId = TIMER_getEventId(mhTimer0); // Get EventId's associated with Timer0 for use with CSL interrupt enable functions
Timer1_eventId = TIMER_getEventId(mhTimer1); // Get EventId's associated with Timer1 for use with CSL interrupt enable functions
mhMcbsp = MCBSP_open(MCBSP_PORT1, MCBSP_OPEN_RESET); // Open MCBSP Port 1 and set registers to their power on defaults
mhDmaRcv = DMA_open(DMA_CHA0,DMA_OPEN_RESET); // Open DMA Channel 0 and set registers to their power on defaults
DMA_rcvEventId = DMA_getEventId(mhDmaRcv); // Get EventId's associated with DMA Channel 0 receive for use with CSL interrupt enable functions
/* Initialize IRQ */
IRQ_globalDisable(); // Disable Global IRQ
IRQ_clear(IRQ_EVT_INT0); // Clear INT0 Status Bit
IRQ_clear(IRQ_EVT_INT1); // Clear INT1 Status Bit
IRQ_clear(IRQ_EVT_INT2); // Clear INT2 Status Bit
IRQ_clear(Timer0_eventId); // Clear any pending Timer interrupts
IRQ_clear(Timer1_eventId); // Clear any pending Timer interrupts
IRQ_clear(DMA_rcvEventId); // Clear any pending DMA Channel 0 receiver interrupts
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