ecan.c
来自「DSP2808例程。TMS320F2808DSP的各个模块的应用例程」· C语言 代码 · 共 375 行
C
375 行
#include "DSP280x_Device.h" // DSP280x Headerfile Include File
#include "DSP280x_Examples.h" // DSP280x Examples Include File
extern Uint32 TestMbox1;
extern Uint32 TestMbox2;
extern Uint32 TestMbox3;
struct ECAN_REGS ECanaShadow;
interrupt void ecan0_isr(void)
{//int MIV = 0; //*
asm (" NOP");
PieCtrlRegs.PIEACK.all |= 0x100; // Issue PIE ack
}
//*
interrupt void ecan1_isr(void)
{int MIV = 0;
asm (" NOP");
if(ECanaRegs.CANGIF1.bit.GMIF1)
{
MIV = ECanaRegs.CANGIF1.bit.MIV1;
switch(MIV)
{
case 31:
break;
case 30:
break;
case 2:
if(ECanaRegs.CANRMP.bit.RMP2)
{
ECanaRegs.CANRMP.bit.RMP2 = 1;
//TestMbox7 = ECanaMboxes.MBOX2.MDL.all;
//TestMbox8 = ECanaMboxes.MBOX2.MDH.all;
//TestMbox9 = ECanaMboxes.MBOX2.MSGID.all;
}
break;
case 1:
if(ECanaRegs.CANTA.bit.TA1)
{
ECanaShadow.CANTA.all = 0;
ECanaShadow.CANTA.bit.TA1 = 1;
ECanaRegs.CANTA.all = ECanaShadow.CANTA.all;
}
break;
case 0:
//TestMbox4 = ECanaMboxes.MBOX0.MDL.all;
//TestMbox5 = ECanaMboxes.MBOX0.MDH.all;
//TestMbox6 = ECanaMboxes.MBOX0.MSGID.all;
ECanaRegs.CANRMP.bit.RMP0 = 1;
break;
}
}
PieCtrlRegs.PIEACK.all |= 0x100; // Issue PIE ack
}
//*/
void ecan_mbox_init(void)
{
///*
EALLOW;
// setup tx1
//ECanaMboxes.MBOX1.MSGID.all = 0x95555555;
ECanaMboxes.MBOX1.MSGID.bit.IDE = 0;
ECanaMboxes.MBOX1.MSGID.bit.AME = 0;
ECanaMboxes.MBOX1.MSGID.bit.AAM = 0;
ECanaMboxes.MBOX1.MSGID.bit.STDMSGID = (0x8A<<3);
ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 8;
ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
ECanaShadow.CANMD.bit.MD1 = 0;
ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;
ECanaShadow.CANME.all = ECanaRegs.CANME.all;
ECanaShadow.CANME.bit.ME1 = 1;
ECanaRegs.CANME.all = ECanaShadow.CANME.all;
TestMbox1 = 0xA0A0A0A0;
TestMbox2 = 0x50505050;
ECanaMboxes.MBOX1.MDL.all = TestMbox1;
ECanaMboxes.MBOX1.MDH.all = TestMbox2;
// setup rx0
ECanaMboxes.MBOX0.MSGID.all = 0x9ffffff0;
ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
ECanaShadow.CANMD.bit.MD0 = 1;
ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;
ECanaShadow.CANME.all = ECanaRegs.CANME.all;
ECanaShadow.CANME.bit.ME0 = 1;
ECanaRegs.CANME.all = ECanaShadow.CANME.all;
// setup rx2
//ECanaMboxes.MBOX2.MSGID.all = 0x9fffffff;
//ECanaMboxes.MBOX2.MSGID.all = 0xdffff567;
//ECanaLAMRegs.LAM2.all = 0xFFFFFFF8;
ECanaMboxes.MBOX2.MSGID.bit.IDE = 0;
ECanaMboxes.MBOX2.MSGID.bit.AME = 0;
ECanaMboxes.MBOX2.MSGID.bit.AAM = 0;
ECanaMboxes.MBOX2.MSGID.bit.STDMSGID = (0x8B<<3);
//ECanaLAMRegs.LAM2.bit.LAMI = 1;
//ECanaLAMRegs.LAM2.bit.LAM_H= 0x;
//ECanaLAMRegs.LAM2.bit.LAM_L=;
ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
ECanaShadow.CANMD.bit.MD2 = 1;
ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;
ECanaShadow.CANME.all = ECanaRegs.CANME.all;
ECanaShadow.CANME.bit.ME2 = 1;
ECanaRegs.CANME.all = ECanaShadow.CANME.all;
// Configure CAN interrupts
ECanaShadow.CANMIL.all = 0xFFFFFFFF ; // Interrupts asserted on eCAN1INT
//ECanaShadow.CANMIL.all = 0x00000000 ; // Interrupts asserted on eCAN0INT
ECanaRegs.CANMIL.all = ECanaShadow.CANMIL.all;
ECanaShadow.CANMIM.all = 0x07;//0xFFFFFFFF; // Enable interrupts for all mailboxes
ECanaRegs.CANMIM.all = ECanaShadow.CANMIM.all;
//ECanaShadow.CANGIM.all = 0xFFFFFFFF;
ECanaShadow.CANGIM.bit.I0EN = 0; // Enable eCAN1INT or eCAN0INT
ECanaShadow.CANGIM.bit.I1EN = 1;
ECanaShadow.CANGIM.bit.GIL = 0;
ECanaRegs.CANGIM.all = ECanaShadow.CANGIM.all;
EDIS;
}
void InitECana(void) // Initialize eCAN-A module
{
/* Create a shadow register structure for the CAN control registers. This is
needed, since, only 32-bit access is allowed to these registers. 16-bit access
to these registers could potentially corrupt the register contents. This is
especially true while writing to a bit (or group of bits) among bits 16 - 31 */
struct ECAN_REGS ECanaShadow;
EALLOW; // EALLOW enables access to protected bits
/* Configure eCAN RX and TX pins for eCAN transmissions using eCAN regs*/
ECanaRegs.CANTIOC.bit.TXFUNC = 1;
ECanaRegs.CANRIOC.bit.RXFUNC = 1;
/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */
// HECC mode also enables time-stamping feature
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.SCB = 1;
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
/* Initialize all bits of 'Master Control Field' to zero */
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MSGCTRL must be initialized to zero
ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;
// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
// as a matter of precaution.
ECanaRegs.CANTA.all = 0xFFFFFFFF; /* Clear all TAn bits */
ECanaRegs.CANRMP.all = 0xFFFFFFFF; /* Clear all RMPn bits */
ECanaRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */
ECanaRegs.CANGIF1.all = 0xFFFFFFFF;
/* Configure bit timing parameters for eCANA*/
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
while(ECanaRegs.CANES.bit.CCE != 1 ) {} // Wait for CCE bit to be set..
ECanaShadow.CANBTC.all = 0;
ECanaShadow.CANBTC.bit.BRPREG = 79;
ECanaShadow.CANBTC.bit.TSEG2REG = 1;
ECanaShadow.CANBTC.bit.TSEG1REG = 6;
ECanaShadow.CANBTC.bit.SAM = 1;
ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;
ECanaShadow.CANGAM.all = ECanaRegs.CANGAM.all;
ECanaShadow.CANGAM.bit.AMI = 1;
ECanaRegs.CANGAM.all = ECanaShadow.CANGAM.all;
//ECanaRegs.CANGAM.all = 0xFFFFFFFF;
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
while(ECanaRegs.CANES.bit.CCE == !0 ) {} // Wait for CCE bit to be cleared..
/* Disable all Mailboxes */
ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs
EDIS;
ecan_mbox_init();
}
//---------------------------------------------------------------------------
// Example: InitECanGpio:
//---------------------------------------------------------------------------
// This function initializes GPIO pins to function as eCAN pins
//
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
// peripheral functional pins. By default all pins come up as GPIO
// inputs after reset.
//
// Caution:
// Only one GPIO pin should be enabled for CANTXA/B operation.
// Only one GPIO pin shoudl be enabled for CANRXA/B operation.
// Comment out other unwanted lines.
void InitECanGpio(void)
{
InitECanaGpio();
#if DSP28_2808
InitECanbGpio();
#endif // if DSP28_2808
}
void InitECanaGpio(void)
{
EALLOW;
/* Enable internal pull-up for the selected CAN pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; // Enable pull-up for GPIO30 (CANRXA)
GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; // Enable pull-up for GPIO31 (CANTXA)
/* Set qualification for selected CAN pins to asynch only */
// Inputs are synchronized to SYSCLKOUT by default.
// This will select asynch (no qualification) for the selected pins.
GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3; // Asynch qual for GPIO30 (CANRXA)
/* Configure eCAN-A pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be eCAN functional pins.
GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // Configure GPIO30 for CANTXA operation
GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // Configure GPIO31 for CANRXA operation
EDIS;
}
#if DSP28_2808
void InitECanbGpio(void)
{
EALLOW;
/* Enable internal pull-up for the selected CAN pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; // Enable pull-up for GPIO8 (CANTXB)
// GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pull-up for GPIO12 (CANTXB)
// GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up for GPIO16 (CANTXB)
// GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pull-up for GPIO20 (CANTXB)
GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Enable pull-up for GPIO10 (CANRXB)
// GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pull-up for GPIO13 (CANRXB)
// GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up for GPIO17 (CANRXB)
// GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pull-up for GPIO21 (CANRXB)
/* Set qualification for selected CAN pins to asynch only */
// Inputs are synchronized to SYSCLKOUT by default.
// This will select asynch (no qualification) for the selected pins.
// Comment out other unwanted lines.
GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 3; // Asynch qual for GPIO10 (CANRXB)
// GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch qual for GPIO13 (CANRXB)
// GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch qual for GPIO17 (CANRXB)
// GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; // Asynch qual for GPIO21 (CANRXB)
/* Configure eCAN-B pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be eCAN functional pins.
GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 2; // Configure GPIO8 for CANTXB operation
// GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 2; // Configure GPIO12 for CANTXB operation
// GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 2; // Configure GPIO16 for CANTXB operation
// GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 3; // Configure GPIO20 for CANTXB operation
GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 2; // Configure GPIO10 for CANRXB operation
// GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 2; // Configure GPIO13 for CANRXB operation
// GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 2; // Configure GPIO17 for CANRXB operation
// GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 3; // Configure GPIO21 for CANRXB operation
EDIS;
}
#endif // if DSP28_2808
/***************************************************/
/* Bit configuration parameters for 100 MHz SYSCLKOUT*/
/***************************************************/
/*
The table below shows how BRP(reg) field must be changed to achieve different bit
rates with a BT of 10, for a 80% SP:
---------------------------------------------------
BT = 10, TSEG1 = 6, TSEG2 = 1, Sampling Point = 80%
---------------------------------------------------
1 Mbps : BRP(reg)+1 = 10 : CAN clock = 10 MHz
500 kbps : BRP(reg)+1 = 20 : CAN clock = 5 MHz
250 kbps : BRP(reg)+1 = 40 : CAN clock = 2.5 MHz
125 kbps : BRP(reg)+1 = 80 : CAN clock = 1.25 MHz
100 kbps : BRP(reg)+1 = 100 : CAN clock = 1 MHz
50 kbps : BRP(reg)+1 = 200 : CAN clock = 0.5 MHz
The table below shows how to achieve different sampling points with a BT of 20:
-------------------------------------------------------------
Achieving desired SP by changing TSEG1 & TSEG2 with BT = 20
-------------------------------------------------------------
TSEG1 = 15, TSEG2 = 2, SP = 85%
TSEG1 = 14, TSEG2 = 3, SP = 80%
TSEG1 = 13, TSEG2 = 4, SP = 75%
TSEG1 = 12, TSEG2 = 5, SP = 70%
TSEG1 = 11, TSEG2 = 6, SP = 65%
TSEG1 = 10, TSEG2 = 7, SP = 60%
The table below shows how BRP(reg) field must be changed to achieve different bit
rates with a BT of 20, for the sampling points shown above:
1 Mbps : BRP(reg)+1 = 5
500 kbps : BRP(reg)+1 = 10
250 kbps : BRP(reg)+1 = 20
125 kbps : BRP(reg)+1 = 40
100 kbps : BRP(reg)+1 = 50
50 kbps : BRP(reg)+1 = 100
*/
//===========================================================================
// End of file.
//===========================================================================
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