myvalues.h

linux plx9054芯片驱动程序 设备为一块只写PMC板

#ifndef __MYVALUES_H
#define __MYVALUES_H
#define REG_EEPROM_CTRL                 0x006C
#define REG_MCU_Ctl                     0x00180700
#define REG_Task_Output                 0x00180704
#define REG_Task_outlen                 0x0018070B-0x00180704
#define REG_Task_Input                  0x001807F0
#define REG_Task_inlen                  0x001807F7-0x001807F0
#define  U32  unsigned  int
#define  U16  unsigned  short
#define  S32  int
#define  S16  short  int
#define  U8   unsigned  char
#define  S8   char

#include <linux/ioctl.h>
#undef PDEBUG
#ifdef PMCDA_DEBUG
#ifdef __KERNEL__
#define PDEBUG(fmt,args...) printk(KERN_EMERG "PMCDA:"fmt,##args)
#else 
#define PDEBUG(fmt,args) fprintf(stderr,fmt,##args)
#endif 
#else
#define PDEBUG(FMT,ARGS...)
#endif
#undef PDEBUGG
#define PDEBUGG(fmt,args...)



#define PCI_PTADMA0_AHBADDR_OFFSET		0x58
#define PCI_PTADMA0_PCIADDR_OFFSET		0x5C
#define PCI_PTADMA0_LENADDR_OFFSET		0x60
#define PCI_PTADMA1_AHBADDR_OFFSET		0x64
#define PCI_PTADMA1_PCIADDR_OFFSET		0x68
#define PCI_PTADMA1_LENADDR_OFFSET		0x6C




#define PCI_PTADMA0_AHBADDR				IXP4XX_PCI_CSR(PCI_PTADMA0_AHBADDR_OFFSET)
#define PCI_PTADMA0_PCIADDR				IXP4XX_PCI_CSR(PCI_PTADMA0_PCIADDR_OFFSET)
#define PCI_PTADMA0_LENADDR				IXP4XX_PCI_CSR(PCI_PTADMA0_LENADDR_OFFSET)
#define PCI_PTADMA1_AHBADDR				IXP4XX_PCI_CSR(PCI_PTADMA1_AHBADDR_OFFSET)
#define PCI_PTADMA1_PCIADDR				IXP4XX_PCI_CSR(PCI_PTADMA1_PCIADDR_OFFSET)
#define PCI_PTADMA1_LENADDR				IXP4XX_PCI_CSR(PCI_PTADMA1_LENADDR_OFFSET)
struct iomem
{
  unsigned long     offset;
  unsigned long     *value;
  unsigned long     datawid;
  unsigned long     datasiz;
  unsigned long     tasktype;
  unsigned long     taskstat;
  unsigned long     len;
};

struct FpgaRegister
{
        unsigned long offset;
        unsigned long value;
};




extern unsigned long base;
extern void *pciMem;
//#define PLX_REG_READ              readl
#define PLX_REG_READ(offset)   readl((unsigned long)pciMem+offset)   
#define PLX_REG_WRITE(value)      writel((value),REG_EEPROM_CTRL+(unsigned long)pciMem) 
/*****************************************\
 * |*       IOCTL MACRO DEFINITIONS         *|)
#define SET_DMA_CH0_SIZE _IOW(PCI9054_IOC_MAGIC, 4, unsigned int *)
 * \*****************************************/
#define PCI9054_IOC_MAGIC 'k'
#define WR_FPGA_REGISTER _IOW(PCI9054_IOC_MAGIC, 0, struct FpgaRegister *)
#define RD_FPGA_REGISTER _IOWR(PCI9054_IOC_MAGIC, 1, struct FpgaRegister *)
#define DMA_CH0_RECV_CTRL _IO(PCI9054_IOC_MAGIC, 2)
#define DMA_CH1_SEND_CTRL _IO(PCI9054_IOC_MAGIC, 3)
#define SET_DMA_SIZE _IOW(PCI9054_IOC_MAGIC, 4, unsigned int *)
#define WR_EEPROM _IOW(PCI9054_IOC_MAGIC, 5, struct FpgaRegister *)
#define RD_EEPROM _IOWR(PCI9054_IOC_MAGIC, 6, struct FpgaRegister *)
#define RD_REG _IOWR(PCI9054_IOC_MAGIC, 7, struct FpgaRegister *)
#define RD_IOMEM _IOWR(PCI9054_IOC_MAGIC, 8, struct iomem *)
#define WR_IOMEM _IOW(PCI9054_IOC_MAGIC, 9, struct   iomem *)
#define FFT_WRITE _IOW(PCI9054_IOC_MAGIC,10,struct iomem *)
#define DFT_WRITE _IOW(PCI9054_IOC_MAGIC,11,struct iomem *)
#define FHT_WRITE _IOW(PCI9054_IOC_MAGIC,12,struct iomem *)
#define CON_WRITE _IOW(PCI9054_IOC_MAGIC,13,struct iomem *)
#define PRO_WRITE _IOW(PCI9054_IOC_MAGIC,14,struct iomem *)
#define FFT_WRITE _IOW(PCI9054_IOC_MAGIC,15,struct iomem *)
#define PCI9054_IOC_MAXNR 16

#define BUF_SIZE 0x4000

/*****************************************\
 * |*       IOCTL MACRO DEFINITIONS         *|
 * \*****************************************/
#define VENDORID 0x10B5 // unsigned short for vendor id of the PCI card
#define DEVICEID 0x1112 // unsigned short for device id of the PCI card

#endif



/**********************************************
*               Definitions
**********************************************/
// EEPROM definitions
#define EE66_CMD_LEN                    11      // Bits in instructions
#define EE_READ                         0x0180  // 01 1000 0000 read instruction
#define EE_WRITE                        0x0140  // 01 0100 0000 write instruction
#define EE_WREN                         0x0130  // 01 0011 0000 write enable instruction
#define EE_WRALL                        0x0110  // 01 0001 0000 write all registers
#define EE_PRREAD                       0x0180  // 01 1000 0000 read address stored in Protect Register
#define EE_PRWRITE                      0x0140  // 01 0100 0000 write the address into PR
#define EE_WDS                          0x0100  // 01 0000 0000 write disable instruction
#define EE_PREN                         0x0130  // 01 0011 0000 protect enable instruction
#define EE_PRCLEAR                      0x01FF  // 01 1111 1111 clear protect register instr
#define EE_PRDS                         0x0100  // 01 0000 0000 ONE TIME ONLY, permenant */

//arm ctl
#define DATAWIDTH                       22
#define DATASIZE                        11
#define TASKTYPE                        0
#define CTLFFT                          100
#define CTLDFT                          101
#define CTLFHT									 110
#define CTLCON								    111
#define CTLPRO									 001


unsigned long EepromRead( U16  offset);

void  EepromWrite(U32  value ,U16 offset);