m500auc.c

射频卡读卡头的程序

            WriteRawIO(RegInterruptRq,0x20); // disable Timer IRQ request
            irqBits &= ~0x20;   // clear Timer IRQ in local var
            MpIsrInfo->irqSource &= ~0x20; // clear Timer IRQ in info var
                                        // when idle received, then cancel
                                        // timeout
            WriteRawIO(RegInterruptRq,0x04);  // reset IRQ bit
            // status should still be MI_OK
            // no error - only used for wake up
         }

         //************* TimerIRQ Handling ***********
         if (irqBits & 0x20)       // timer IRQ
         {
            WriteRawIO(RegInterruptRq,0x20); // reset IRQ bit
            MpIsrInfo->status = MI_NOTAGERR; // timeout error
                                             // otherwise ignore the interrupt
         }

      }
   }
}

///////////////////////////////////////////////////////////////////////
//         S e t   T i m e o u t   L E N G T H
///////////////////////////////////////////////////////////////////////
void M500PcdSetTmo(unsigned char tmoLength)
{
   switch(tmoLength)
   {  // timer clock frequency 13,56 MHz
      case 1:                       // short timeout (1,0 ms)
         WriteIO(RegTimerClock,0x07); // TAutoRestart=0,TPrescale=128
         WriteIO(RegTimerReload,0x6a);// TReloadVal = 'h6a =106(dec)
         break;
      case 2:                       // medium timeout (1,5 ms)
         WriteIO(RegTimerClock,0x07); // TAutoRestart=0,TPrescale=128
         WriteIO(RegTimerReload,0xa0);// TReloadVal = 'ha0 =160(dec)
         break;
      case 3:                       // medium timeout (6 ms)
         WriteIO(RegTimerClock,0x09); // TAutoRestart=0,TPrescale=4*128
         WriteIO(RegTimerReload,0xa0);// TReloadVal = 'ha0 =160(dec)
         break;
      case 4:                       // long timeout (9.6 ms)
         WriteIO(RegTimerClock,0x09); // TAutoRestart=0,TPrescale=4*128
         WriteIO(RegTimerReload,0xff);// TReloadVal = 'hff =255(dec)
         break;
      case 5:                       // long timeout (38.5 ms)
         WriteIO(RegTimerClock,0x0b); // TAutoRestart=0,TPrescale=16*128
         WriteIO(RegTimerReload,0xff);// TReloadVal = 'hff =255(dec)
         break;
      case 6:                       // long timeout (154 ms)
         WriteIO(RegTimerClock,0x0d); // TAutoRestart=0,TPrescale=64*128
         WriteIO(RegTimerReload,0xff);// TReloadVal = 'hff =255(dec)
         break;
      case 7:                       // long timeout (616.2 ms)
         WriteIO(RegTimerClock,0x0f); // TAutoRestart=0,TPrescale=256*128
         WriteIO(RegTimerReload,0xff);// TReloadVal = 'hff =255(dec)
         break;
      default:                       //
         WriteIO(RegTimerClock,0x07); // TAutoRestart=0,TPrescale=128
         WriteIO(RegTimerReload,tmoLength);// TReloadVal = 'h6a =tmoLength(dec)
         break;
   }
}

//////////////////////////////////////////////////////////////////////
//       W R I T E   A   P C D   C O M M A N D
///////////////////////////////////////////////////////////////////////
char  M500PcdCmd(unsigned char cmd,
               volatile unsigned char* send,
               volatile unsigned char* rcv,
               volatile MfCmdInfo *info)
{
   char          data status    = MI_OK;
   char          data tmpStatus ;
   unsigned char data lastBits;

   unsigned char data irqEn     = 0x00;
   unsigned char data waitFor   = 0x00;
   unsigned char data timerCtl  = 0x00;
   delay_50us(100);
   WriteIO(0x0,0x0);
   WriteIO(RegIRqPinConfig,0x03);

   Temp = ReadIO(RegIRqPinConfig);
   WriteIO(RegInterruptEn,0x7F); // disable all interrupts
   Temp = ReadIO(RegInterruptEn);
   WriteIO(RegInterruptRq,0x7F); // reset interrupt requests
   Temp = ReadIO(RegInterruptRq);
   WriteIO(RegCommand,PCD_IDLE); // terminate probably running command
   Temp = ReadIO(RegCommand);
   FlushFIFO();            // flush FIFO buffer

   // save info structures to module pointers
   MpIsrInfo = info;
   MpIsrOut  = send;
   MpIsrIn   = rcv;

   info->irqSource = 0x0; // reset interrupt flags
   // depending on the command code, appropriate interrupts are enabled (irqEn)
   // and the commit interrupt is choosen (waitFor).
   switch(cmd)
   {
      case PCD_IDLE:                   // nothing else required cmd code: 0x00
         irqEn = 0x00;
         waitFor = 0x00;
         break;
      case PCD_WRITEE2:                // LoAlert and TxIRq     cmd code: 0x01 
         irqEn = 0x11;
         waitFor = 0x10;
         break;
      case PCD_READE2:                 // HiAlert, LoAlert and IdleIRq  cmd code: 0x03
         irqEn = 0x07;
         waitFor = 0x04;
         break;
      case PCD_LOADCONFIG:             // IdleIRq   cmd code: 0x07
      case PCD_LOADKEYE2:              // IdleIRq   cmd code: 0x0b
      case PCD_AUTHENT1:               // IdleIRq   cmd code: 0x0c
         irqEn = 0x05;
         waitFor = 0x04;
         break;
      case PCD_CALCCRC:                // LoAlert and TxIRq  cmd code: 0x12
         irqEn = 0x11;
         waitFor = 0x10;
         break;
      case PCD_AUTHENT2:               // IdleIRq  cmd code: 0x14
         irqEn = 0x04;
         waitFor = 0x04;
         break;
      case PCD_RECEIVE:                // HiAlert and IdleIRq  cmd code: 0x16
         info->nBitsReceived = -(ReadIO(RegBitFraming) >> 4);  
         irqEn = 0x06;
         waitFor = 0x04;
         break;
      case PCD_LOADKEY:                // IdleIRq   cmd code: 0x19
         irqEn = 0x05;
         waitFor = 0x04;
         break;
      case PCD_TRANSMIT:               // LoAlert and IdleIRq cmd code: 0x1a
         irqEn = 0x05;
         waitFor = 0x04;
         break;
      case PCD_TRANSCEIVE:             // TxIrq, RxIrq, IdleIRq and LoAlert  cmd code: 0x1e
	 info->nBitsReceived = -(ReadIO(RegBitFraming) >> 4);
         irqEn = 0x3D;
         waitFor = 0x04;
         break;
      default:
         status = MI_UNKNOWN_COMMAND;
   }
   if (status == MI_OK)
   {
      // Initialize uC Timer for global Timeout management
      irqEn |= 0x20;                        // always enable timout irq
      waitFor |= 0x20;                      // always wait for timeout
      Temp = ReadIO(RegInterruptEn);
      start_timeout(4000);          // initialise and start guard timer for reader
      				    // 50us resolution, 200ms

      WriteIO(RegInterruptEn,irqEn | 0x80);  //necessary interrupts are enabled
      WriteIO(RegCommand,cmd);               //start command

      // wait for commmand completion
      // a command is completed, if the corresponding interrupt occurs
      // or a timeout is signaled

      while (!(MpIsrInfo->irqSource & waitFor
               || T2IR));                // wait for cmd completion or timeout

      WriteIO(RegInterruptEn,0x7F);          // disable all interrupts
      WriteIO(RegInterruptRq,0x7F);          // clear all interrupt requests
      SetBitMask(RegControl,0x04);           // stop timer now

      stop_timeout();  			// stop timeout for reader
      WriteIO(RegCommand,PCD_IDLE);          // reset command register


      if (!(MpIsrInfo->irqSource & waitFor))   // reader has not terminated
      {                                // timer 2 expired
         status = MI_ACCESSTIMEOUT;
      }
      else
         status = MpIsrInfo->status;           // set status

      if (status == MI_OK)                     // no timeout error occured
      {
         if (tmpStatus = (ReadIO(RegErrorFlag) & 0x17)) // error occured
         {
            if (tmpStatus & 0x01)   // collision detected
            {
               info->collPos = ReadIO(RegCollpos); // read collision position
               status = MI_COLLERR;
            }
            else
            {
               info->collPos = 0;
               if (tmpStatus & 0x02)   // parity error
               {
                  status = MI_PARITYERR;
               }
            }
            if (tmpStatus & 0x04)   // framing error
            {
               status = MI_FRAMINGERR;
            }
            if (tmpStatus & 0x10)   // FIFO overflow
            {
               FlushFIFO();
               status = MI_OVFLERR;
            }
 	        if (tmpStatus & 0x08) //CRC error
	        {
               status = MI_CRCERR;
	        }
            if (status == MI_OK)
               status = MI_NY_IMPLEMENTED;
            // key error occures always, because of
            // missing crypto 1 keys loaded
         }
         // if the last command was TRANSCEIVE, the number of
         // received bits must be calculated - even if an error occured
         if (cmd == PCD_TRANSCEIVE)
         {
            // number of bits in the last byte
            lastBits = ReadIO(RegSecondaryStatus) & 0x07;
            if (lastBits)
               info->nBitsReceived += (info->nBytesReceived-1) * 8 + lastBits;
            else
               info->nBitsReceived += info->nBytesReceived * 8;
         }
      }
      else
      {
         info->collPos = 0x00;
      }
   }
   MpIsrInfo = 0;         // reset interface variables for ISR
   MpIsrOut  = 0;
   MpIsrIn   = 0;
   return status;
}

//////////////////////////////////////////////////////////////////////
//   S E T   A   B I T   M A S K
///////////////////////////////////////////////////////////////////////
char SetBitMask(unsigned char reg,unsigned char mask) //
{
   char data tmp = 0x0;

   tmp = ReadIO(reg);
   WriteIO(reg,tmp | mask);  // set bit mask
   return 0x0;
}

//////////////////////////////////////////////////////////////////////
//   C L E A R   A   B I T   M A S K
///////////////////////////////////////////////////////////////////////
char ClearBitMask(unsigned char reg,unsigned char mask) //
{
   char data tmp = 0x0;

   tmp = ReadIO(reg);
   WriteIO(reg,tmp & ~mask);  // clear bit mask
   return 0x0;
}

///////////////////////////////////////////////////////////////////////
//                  F L U S H    F I F O
///////////////////////////////////////////////////////////////////////
void FlushFIFO(void)
{
   SetBitMask(RegControl,0x01);
}

///////////////////////////////////////////////////////////////////////
//      M I F A R E   M O D U L E   R E S E T
///////////////////////////////////////////////////////////////////////
char M500PcdReset(void)
{
   char data status = MI_OK;

   RC500RST = FALSE;  // clear reset pin
   delay_1ms(25);  // wait for 25ms
   RC500RST = TRUE;   // reset RC500
   delay_50us(50);  // wait for 2.5ms
   RC500RST = FALSE;  // clear reset pin

   start_timeout(42000); 	// count down with a period of 50 us
   			        // 42000 * 50 us = 2.1 s
  // Temp = ReadRawIO(RegCommand);

  // wait until reset command recognized
   while (((ReadRawIO(RegCommand) & 0x3F) != 0x3F) && !T2IR);//读出复位命令码0x3f
   // while reset sequence in progress
   while ((ReadRawIO(RegCommand) & 0x3F) && !T2IR);//复位成功后读出数为0


   stop_timeout();  		// stop timeout counter

   if (T2IR) 		// If reader timeout occurs
   {
      status = MI_RESETERR; // respose of reader IC is not correct
      T2IR   = 0;
   }
   else
   {

   // configure to linear address mode  配置成线性地址模式

      WriteIO(0x00,0x00);
      WriteIO(0x08,0x00);
      WriteIO(0x10,0x00);
      WriteIO(0x18,0x00);
      WriteIO(0x20,0x00);
      WriteIO(0x28,0x00);
      WriteIO(0x30,0x00);
      WriteIO(0x38,0x00);

   }
   return status;
}

///////////////////////////////////////////////////////////////////////
//      M I F A R E   M O D U L E   C O N F I G U R A T I O N
///////////////////////////////////////////////////////////////////////
char M500PcdConfig(void)
{
   char data status;
   char data i;
   char data j;

   if ((status = M500PcdReset()) == MI_OK)
   {
     delay_50us(100);

     WriteIO(0x0,0x0);
     // test clock Q calibration - value in the range of 0x46 expected
     WriteIO(RegClockQControl,0x0);

     Temp = ReadIO(RegClockQControl);

     WriteIO(RegClockQControl,0x40);

     Temp = ReadIO(RegClockQControl);

     delay_50us(2);  // wait approximately 100 us - calibration in progress
     ClearBitMask(RegClockQControl,0x40); // clear bit ClkQCalib for
                                          // further calibration

     // The following values for RegBitPhase and
     // RegRxThreshold represents an optimal
     // value for our demo package. For user
     // implementation some changes could be
     // necessary
     // initialize bit phase


     WriteIO(RegBitPhase,0xAD);

     Temp = ReadIO(RegBitPhase);

     // initialize minlevel
     WriteIO(RegRxThreshold,0xFF);