📄 m500auc.lst
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472 2 break;
473 2 case PCD_READE2: // HiAlert, LoAlert and IdleIRq cmd code: 0x03
474 2 irqEn = 0x07;
475 2 waitFor = 0x04;
476 2 break;
477 2 case PCD_LOADCONFIG: // IdleIRq cmd code: 0x07
478 2 case PCD_LOADKEYE2: // IdleIRq cmd code: 0x0b
479 2 case PCD_AUTHENT1: // IdleIRq cmd code: 0x0c
480 2 irqEn = 0x05;
481 2 waitFor = 0x04;
482 2 break;
483 2 case PCD_CALCCRC: // LoAlert and TxIRq cmd code: 0x12
484 2 irqEn = 0x11;
485 2 waitFor = 0x10;
486 2 break;
487 2 case PCD_AUTHENT2: // IdleIRq cmd code: 0x14
488 2 irqEn = 0x04;
489 2 waitFor = 0x04;
490 2 break;
491 2 case PCD_RECEIVE: // HiAlert and IdleIRq cmd code: 0x16
492 2 info->nBitsReceived = -(ReadIO(RegBitFraming) >> 4);
493 2 irqEn = 0x06;
494 2 waitFor = 0x04;
495 2 break;
496 2 case PCD_LOADKEY: // IdleIRq cmd code: 0x19
497 2 irqEn = 0x05;
498 2 waitFor = 0x04;
499 2 break;
500 2 case PCD_TRANSMIT: // LoAlert and IdleIRq cmd code: 0x1a
501 2 irqEn = 0x05;
502 2 waitFor = 0x04;
503 2 break;
504 2 case PCD_TRANSCEIVE: // TxIrq, RxIrq, IdleIRq and LoAlert cmd code: 0x1e
505 2 info->nBitsReceived = -(ReadIO(RegBitFraming) >> 4);
506 2 irqEn = 0x3D;
507 2 waitFor = 0x04;
508 2 break;
509 2 default:
510 2 status = MI_UNKNOWN_COMMAND;
511 2 }
512 1 if (status == MI_OK)
513 1 {
514 2 // Initialize uC Timer for global Timeout management
515 2 irqEn |= 0x20; // always enable timout irq
516 2 waitFor |= 0x20; // always wait for timeout
517 2 Temp = ReadIO(RegInterruptEn);
C51 COMPILER V4.01, M500AUC 29/08/06 08:02:01 PAGE 9
518 2 start_timeout(4000); // initialise and start guard timer for reader
519 2 // 50us resolution, 200ms
520 2
521 2 WriteIO(RegInterruptEn,irqEn | 0x80); //necessary interrupts are enabled
522 2 WriteIO(RegCommand,cmd); //start command
523 2
524 2 // wait for commmand completion
525 2 // a command is completed, if the corresponding interrupt occurs
526 2 // or a timeout is signaled
527 2
528 2 while (!(MpIsrInfo->irqSource & waitFor
529 2 || T2IR)); // wait for cmd completion or timeout
530 2
531 2 WriteIO(RegInterruptEn,0x7F); // disable all interrupts
532 2 WriteIO(RegInterruptRq,0x7F); // clear all interrupt requests
533 2 SetBitMask(RegControl,0x04); // stop timer now
534 2
535 2 stop_timeout(); // stop timeout for reader
536 2 WriteIO(RegCommand,PCD_IDLE); // reset command register
537 2
538 2
539 2 if (!(MpIsrInfo->irqSource & waitFor)) // reader has not terminated
540 2 { // timer 2 expired
541 3 status = MI_ACCESSTIMEOUT;
542 3 }
543 2 else
544 2 status = MpIsrInfo->status; // set status
545 2
546 2 if (status == MI_OK) // no timeout error occured
547 2 {
548 3 if (tmpStatus = (ReadIO(RegErrorFlag) & 0x17)) // error occured
549 3 {
550 4 if (tmpStatus & 0x01) // collision detected
551 4 {
552 5 info->collPos = ReadIO(RegCollpos); // read collision position
553 5 status = MI_COLLERR;
554 5 }
555 4 else
556 4 {
557 5 info->collPos = 0;
558 5 if (tmpStatus & 0x02) // parity error
559 5 {
560 6 status = MI_PARITYERR;
561 6 }
562 5 }
563 4 if (tmpStatus & 0x04) // framing error
564 4 {
565 5 status = MI_FRAMINGERR;
566 5 }
567 4 if (tmpStatus & 0x10) // FIFO overflow
568 4 {
569 5 FlushFIFO();
570 5 status = MI_OVFLERR;
571 5 }
572 4 if (tmpStatus & 0x08) //CRC error
573 4 {
574 5 status = MI_CRCERR;
575 5 }
576 4 if (status == MI_OK)
577 4 status = MI_NY_IMPLEMENTED;
578 4 // key error occures always, because of
579 4 // missing crypto 1 keys loaded
580 4 }
581 3 // if the last command was TRANSCEIVE, the number of
582 3 // received bits must be calculated - even if an error occured
583 3 if (cmd == PCD_TRANSCEIVE)
C51 COMPILER V4.01, M500AUC 29/08/06 08:02:01 PAGE 10
584 3 {
585 4 // number of bits in the last byte
586 4 lastBits = ReadIO(RegSecondaryStatus) & 0x07;
587 4 if (lastBits)
588 4 info->nBitsReceived += (info->nBytesReceived-1) * 8 + lastBits;
589 4 else
590 4 info->nBitsReceived += info->nBytesReceived * 8;
591 4 }
592 3 }
593 2 else
594 2 {
595 3 info->collPos = 0x00;
596 3 }
597 2 }
598 1 MpIsrInfo = 0; // reset interface variables for ISR
599 1 MpIsrOut = 0;
600 1 MpIsrIn = 0;
601 1 return status;
602 1 }
603
604 //////////////////////////////////////////////////////////////////////
605 // S E T A B I T M A S K
606 ///////////////////////////////////////////////////////////////////////
607 char SetBitMask(unsigned char reg,unsigned char mask) //
608 {
609 1 char data tmp = 0x0;
610 1
611 1 tmp = ReadIO(reg);
612 1 WriteIO(reg,tmp | mask); // set bit mask
613 1 return 0x0;
614 1 }
615
616 //////////////////////////////////////////////////////////////////////
617 // C L E A R A B I T M A S K
618 ///////////////////////////////////////////////////////////////////////
619 char ClearBitMask(unsigned char reg,unsigned char mask) //
620 {
621 1 char data tmp = 0x0;
622 1
623 1 tmp = ReadIO(reg);
624 1 WriteIO(reg,tmp & ~mask); // clear bit mask
625 1 return 0x0;
626 1 }
627
628 ///////////////////////////////////////////////////////////////////////
629 // F L U S H F I F O
630 ///////////////////////////////////////////////////////////////////////
631 void FlushFIFO(void)
632 {
633 1 SetBitMask(RegControl,0x01);
634 1 }
635
636 ///////////////////////////////////////////////////////////////////////
637 // M I F A R E M O D U L E R E S E T
638 ///////////////////////////////////////////////////////////////////////
639 char M500PcdReset(void)
640 {
641 1 char data status = MI_OK;
642 1
643 1 RC500RST = FALSE; // clear reset pin
644 1 delay_1ms(25); // wait for 25ms
645 1 RC500RST = TRUE; // reset RC500
646 1 delay_50us(50); // wait for 2.5ms
647 1 RC500RST = FALSE; // clear reset pin
648 1
649 1 start_timeout(42000); // count down with a period of 50 us
C51 COMPILER V4.01, M500AUC 29/08/06 08:02:01 PAGE 11
650 1 // 42000 * 50 us = 2.1 s
651 1 // Temp = ReadRawIO(RegCommand);
652 1
653 1 // wait until reset command recognized
654 1 while (((ReadRawIO(RegCommand) & 0x3F) != 0x3F) && !T2IR);//读出复位命令码0x3f
655 1 // while reset sequence in progress
656 1 while ((ReadRawIO(RegCommand) & 0x3F) && !T2IR);//复位成功后读出数为0
657 1
658 1
659 1 stop_timeout(); // stop timeout counter
660 1
661 1 if (T2IR) // If reader timeout occurs
662 1 {
663 2 status = MI_RESETERR; // respose of reader IC is not correct
664 2 T2IR = 0;
665 2 }
666 1 else
667 1 {
668 2
669 2 // configure to linear address mode 配置成线性地址模式
670 2
671 2 WriteIO(0x00,0x00);
672 2 WriteIO(0x08,0x00);
673 2 WriteIO(0x10,0x00);
674 2 WriteIO(0x18,0x00);
675 2 WriteIO(0x20,0x00);
676 2 WriteIO(0x28,0x00);
677 2 WriteIO(0x30,0x00);
678 2 WriteIO(0x38,0x00);
679 2
680 2 }
681 1 return status;
682 1 }
683
684 ///////////////////////////////////////////////////////////////////////
685 // M I F A R E M O D U L E C O N F I G U R A T I O N
686 ///////////////////////////////////////////////////////////////////////
687 char M500PcdConfig(void)
688 {
689 1 char data status;
690 1 char data i;
691 1 char data j;
692 1
693 1 if ((status = M500PcdReset()) == MI_OK)
694 1 {
695 2 delay_50us(100);
696 2
697 2 WriteIO(0x0,0x0);
698 2 // test clock Q calibration - value in the range of 0x46 expected
699 2 WriteIO(RegClockQControl,0x0);
700 2
701 2 Temp = ReadIO(RegClockQControl);
702 2
703 2 WriteIO(RegClockQControl,0x40);
704 2
705 2 Temp = ReadIO(RegClockQControl);
706 2
707 2 delay_50us(2); // wait approximately 100 us - calibration in progress
708 2 ClearBitMask(RegClockQControl,0x40); // clear bit ClkQCalib for
709 2 // further calibration
710 2
711 2 // The following values for RegBitPhase and
712 2 // RegRxThreshold represents an optimal
713 2 // value for our demo package. For user
714 2 // implementation some changes could be
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