📄 m500auc.lst
字号:
232 // mask bit mask to clear
233 // OUT: -
234 // RETURN:
235 // COMMENT: This function performs a read - modify - write sequence
236 // on the specified register. All bits with a 1 in the mask
237 // are cleared - all other bits keep their original value.
238 //
239 char ClearBitMask(unsigned char reg,unsigned char mask);
240
241 // _____________________________________________________________________________
242 //
243 // FUNCTION: FlushFIFO
244 // IN: -
245 // OUT: -
246 // RETURN:
247 // COMMENT: All remaining date in the FIFO of the reader module is
248 // erased by this function. Before wrinting new data or
249 // starting a new command, all remaining data from former
250 // commands should be deleted. Please note, that in
251 // normal operation, never data should be left, that means
252 // that a call to this function should not be necessary.
253 //
254 void FlushFIFO(void);
C51 COMPILER V4.01, M500AUC 29/08/06 08:02:01 PAGE 5
255
256 // _____________________________________________________________________________
257 //
258 // FUNCTION: M500PiccAuthState
259 // IN: auth_mode
260 // snr
261 // sector
262 // OUT: -
263 // RETURN:
264 // COMMENT:
265 //
266 char M500PiccAuthState(unsigned char auth_mode,// PICC_AUTHENT1A, PICC_AUTHENT1B
267 unsigned char *snr, // 4 byte serial number
268 unsigned char sector); // 0 <= sector <= 15
269 // sector address for authentication
270
271 //////////////////////////////////////////////////////////////////////
272 // E X C H A N G E B Y T E S T R E A M
273 ///////////////////////////////////////////////////////////////////////
274 char ExchangeByteStream(unsigned char Cmd,
275 unsigned char *send_data,
276 unsigned char send_bytelen,
277 unsigned char *rec_data,
278 unsigned char *rec_bytelen);
279
280 ///////////////////////////////////////////////////////////////////////////////
281 // Handler RC500
282 // RC500 与Mifare 卡之间的数据通讯由中断服务程序完成
283 // 入口参数: 1. *MpIsrInfo 通讯参数结构指针
284 // 2. *MpIsrout 发送数据指针 send
285 // 3. *MpIsrin 接收数据指针 rec
286 ///////////////////////////////////////////////////////////////////////////////
287 void RC500ISR (void) interrupt 2 using 1 //Ext1 interrupt
288 {
289 1 static uchar data irqBits;
290 1 static uchar data irqMask;
291 1 static uchar data nbytes;
292 1 static uchar data cnt;
293 1
294 1 IE1 = 0; // Clear interrupt request flag
295 1
296 1 if (MpIsrInfo && MpIsrOut && MpIsrIn) // transfer pointers have to be set correctly
297 1 {
298 2 while( ReadRawIO(RegPrimaryStatus) & 0x08) // loop while IRQ pending
299 2 // Attention: IRQ bit is
300 2 // inverted when used with
301 2 // low activ IRQ
302 2 {
303 3 irqMask = ReadRawIO(RegInterruptEn); // read enabled interrupts
304 3 // read pending interrupts
305 3 irqBits = ReadRawIO(RegInterruptRq) & irqMask;//irqBits 表示何种中断
306 3 MpIsrInfo->irqSource |= irqBits; // save pending interrupts
307 3 //************ LoAlertIRQ ******************
308 3 if (irqBits & 0x01) // LoAlert
309 3 {
310 4 // MFIFOLength = DEF_FIFO_LENGTH;
311 4
312 4 nbytes = MFIFOLength - ReadRawIO(RegFIFOLength);//计算FIFO 可以容纳的字节空间
313 4 // less bytes to send, than space in FIFO
314 4
315 4 if ((MpIsrInfo->nBytesToSend - MpIsrInfo->nBytesSent) <= nbytes)//需要发送的字节数<FIFO 可以容
-纳的字节空间 按照需要发送的字节数
316 4 {
317 5 nbytes = MpIsrInfo->nBytesToSend - MpIsrInfo->nBytesSent;//需要发送的字节数
318 5 WriteRawIO(RegInterruptEn,0x01); // disable LoAlert IRQ
319 5 }
C51 COMPILER V4.01, M500AUC 29/08/06 08:02:01 PAGE 6
320 4 // write remaining data to the FIFO
321 4 for ( cnt = 0;cnt < nbytes;cnt++)
322 4 {
323 5 WriteRawIO(RegFIFOData,MpIsrOut[MpIsrInfo->nBytesSent]);
324 5 MpIsrInfo->nBytesSent++;
325 5 }
326 4 WriteRawIO(RegInterruptRq,0x01); // reset IRQ bit
327 4 }
328 3
329 3 //************* TxIRQ Handling **************
330 3 if (irqBits & 0x10) // TxIRQ
331 3 {
332 4 WriteRawIO(RegInterruptRq,0x10); // reset IRQ bit
333 4 WriteRawIO(RegInterruptEn,0x82); // enable HiAlert Irq for
334 4 // response
335 4 if (MpIsrInfo->cmd == PICC_ANTICOLL1) // if cmd is anticollision
336 4 { // switch off parity generation
337 5 WriteRawIO(RegChannelRedundancy,0x02); // RXCRC and TXCRC disable, parity disable
338 5 }
339 4 }
340 3
341 3 //************* HiAlertIRQ or RxIRQ Handling ******************
342 3 if (irqBits & 0x0E) // HiAlert, Idle or RxIRQ
343 3 {
344 4 // read some bytes ( length of FIFO queue)
345 4 // into the receive buffer
346 4 nbytes = ReadRawIO(RegFIFOLength);
347 4 // read date from the FIFO and store them in the receive buffer
348 4 for ( cnt = 0; cnt < nbytes; cnt++)
349 4 {
350 5 MpIsrIn[MpIsrInfo->nBytesReceived] = ReadRawIO(RegFIFOData);
351 5 MpIsrInfo->nBytesReceived++;
352 5 Temp = MpIsrIn[MpIsrInfo->nBytesReceived] ;
353 5 }
354 4 WriteRawIO(RegInterruptRq,0x0A & irqBits);
355 4 // reset IRQ bit - idle irq will
356 4 // be deleted in a seperate section
357 4 }
358 3
359 3 //************** IdleIRQ Handling ***********
360 3 if (irqBits & 0x04) // Idle IRQ
361 3 {
362 4 WriteRawIO(RegInterruptEn,0x20); // disable Timer IRQ
363 4 WriteRawIO(RegInterruptRq,0x20); // disable Timer IRQ request
364 4 irqBits &= ~0x20; // clear Timer IRQ in local var
365 4 MpIsrInfo->irqSource &= ~0x20; // clear Timer IRQ in info var
366 4 // when idle received, then cancel
367 4 // timeout
368 4 WriteRawIO(RegInterruptRq,0x04); // reset IRQ bit
369 4 // status should still be MI_OK
370 4 // no error - only used for wake up
371 4 }
372 3
373 3 //************* TimerIRQ Handling ***********
374 3 if (irqBits & 0x20) // timer IRQ
375 3 {
376 4 WriteRawIO(RegInterruptRq,0x20); // reset IRQ bit
377 4 MpIsrInfo->status = MI_NOTAGERR; // timeout error
378 4 // otherwise ignore the interrupt
379 4 }
380 3
381 3 }
382 2 }
383 1 }
384
385 ///////////////////////////////////////////////////////////////////////
C51 COMPILER V4.01, M500AUC 29/08/06 08:02:01 PAGE 7
386 // S e t T i m e o u t L E N G T H
387 ///////////////////////////////////////////////////////////////////////
388 void M500PcdSetTmo(unsigned char tmoLength)
389 {
390 1 switch(tmoLength)
391 1 { // timer clock frequency 13,56 MHz
392 2 case 1: // short timeout (1,0 ms)
393 2 WriteIO(RegTimerClock,0x07); // TAutoRestart=0,TPrescale=128
394 2 WriteIO(RegTimerReload,0x6a);// TReloadVal = 'h6a =106(dec)
395 2 break;
396 2 case 2: // medium timeout (1,5 ms)
397 2 WriteIO(RegTimerClock,0x07); // TAutoRestart=0,TPrescale=128
398 2 WriteIO(RegTimerReload,0xa0);// TReloadVal = 'ha0 =160(dec)
399 2 break;
400 2 case 3: // medium timeout (6 ms)
401 2 WriteIO(RegTimerClock,0x09); // TAutoRestart=0,TPrescale=4*128
402 2 WriteIO(RegTimerReload,0xa0);// TReloadVal = 'ha0 =160(dec)
403 2 break;
404 2 case 4: // long timeout (9.6 ms)
405 2 WriteIO(RegTimerClock,0x09); // TAutoRestart=0,TPrescale=4*128
406 2 WriteIO(RegTimerReload,0xff);// TReloadVal = 'hff =255(dec)
407 2 break;
408 2 case 5: // long timeout (38.5 ms)
409 2 WriteIO(RegTimerClock,0x0b); // TAutoRestart=0,TPrescale=16*128
410 2 WriteIO(RegTimerReload,0xff);// TReloadVal = 'hff =255(dec)
411 2 break;
412 2 case 6: // long timeout (154 ms)
413 2 WriteIO(RegTimerClock,0x0d); // TAutoRestart=0,TPrescale=64*128
414 2 WriteIO(RegTimerReload,0xff);// TReloadVal = 'hff =255(dec)
415 2 break;
416 2 case 7: // long timeout (616.2 ms)
417 2 WriteIO(RegTimerClock,0x0f); // TAutoRestart=0,TPrescale=256*128
418 2 WriteIO(RegTimerReload,0xff);// TReloadVal = 'hff =255(dec)
419 2 break;
420 2 default: //
421 2 WriteIO(RegTimerClock,0x07); // TAutoRestart=0,TPrescale=128
422 2 WriteIO(RegTimerReload,tmoLength);// TReloadVal = 'h6a =tmoLength(dec)
423 2 break;
424 2 }
425 1 }
426
427 //////////////////////////////////////////////////////////////////////
428 // W R I T E A P C D C O M M A N D
429 ///////////////////////////////////////////////////////////////////////
430 char M500PcdCmd(unsigned char cmd,
431 volatile unsigned char* send,
432 volatile unsigned char* rcv,
433 volatile MfCmdInfo *info)
434 {
435 1 char data status = MI_OK;
436 1 char data tmpStatus ;
437 1 unsigned char data lastBits;
438 1
439 1 unsigned char data irqEn = 0x00;
440 1 unsigned char data waitFor = 0x00;
441 1 unsigned char data timerCtl = 0x00;
442 1 delay_50us(100);
443 1 WriteIO(0x0,0x0);
444 1 WriteIO(RegIRqPinConfig,0x03);
445 1
446 1 Temp = ReadIO(RegIRqPinConfig);
447 1 WriteIO(RegInterruptEn,0x7F); // disable all interrupts
448 1 Temp = ReadIO(RegInterruptEn);
449 1 WriteIO(RegInterruptRq,0x7F); // reset interrupt requests
450 1 Temp = ReadIO(RegInterruptRq);
451 1 WriteIO(RegCommand,PCD_IDLE); // terminate probably running command
C51 COMPILER V4.01, M500AUC 29/08/06 08:02:01 PAGE 8
452 1 Temp = ReadIO(RegCommand);
453 1 FlushFIFO(); // flush FIFO buffer
454 1
455 1 // save info structures to module pointers
456 1 MpIsrInfo = info;
457 1 MpIsrOut = send;
458 1 MpIsrIn = rcv;
459 1
460 1 info->irqSource = 0x0; // reset interrupt flags
461 1 // depending on the command code, appropriate interrupts are enabled (irqEn)
462 1 // and the commit interrupt is choosen (waitFor).
463 1 switch(cmd)
464 1 {
465 2 case PCD_IDLE: // nothing else required cmd code: 0x00
466 2 irqEn = 0x00;
467 2 waitFor = 0x00;
468 2 break;
469 2 case PCD_WRITEE2: // LoAlert and TxIRq cmd code: 0x01
470 2 irqEn = 0x11;
471 2 waitFor = 0x10;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -