📄 cpu.h
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//#define w77e58
#define sst89e554
//#define AT89C51RC
//#define sm8958
/* 8052 Processor Declarations */
/* BYTE Registers */
sfr P0 = 0x80;
sfr P1 = 0x90;
sfr P2 = 0xA0;
sfr P3 = 0xB0;
sfr PSW = 0xD0;
sfr ACC = 0xE0;
sfr B = 0xF0;
sfr SP = 0x81;
sfr DPL = 0x82;
sfr DPH = 0x83;
sfr PCON = 0x87;
sfr TCON = 0x88;
sfr TMOD = 0x89;
sfr TL0 = 0x8A;
sfr TL1 = 0x8B;
sfr TH0 = 0x8C;
sfr TH1 = 0x8D;
sfr IE = 0xA8;
sfr IP = 0xB8;
sfr SCON = 0x98;
sfr SBUF = 0x99;
#ifdef w77e58
sfr EIE = 0xE8;
#endif
#ifdef sst89e554
sfr IEA = 0xE8;
#endif
#ifdef w77e58
/* Special W77e58 Reg */
sfr PMR = 0xC4;
sbit DME0 = 0xC4;
#endif
#ifdef AT89C51RC
/* Special AT89C51RC Reg */
sfr AUXR = 0x8E;
/*
sbit DISALE = AUXR^0;
sbit EXTRAM = AUXR^1;
sbit DISTRO = AUXR^3;
sbit WDIDLE = AUXR^4;
*/
#endif
#ifdef sm8958
//系统控制寄存器 (SCONF: 0xbf)
//----------------------------------------------------------------------------------
//Location | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
//----------------------------------------------------------------------------------
// 0xBF | WDR | 0 | 0 | 0 | 0 | 0 | OME | ALE1 |
//----------------------------------------------------------------------------------
// 复位值 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
//----------------------------------------------------------------------------------
//WDR: 看门狗定时器复位位。当看门狗定时器溢出而使系统复位时，WDR位被置1
//OME: 768片上字节使能位
//ALE1: ALE输出禁止位，可降低EMI
sfr SCONF = 0xBF;
//Watchdog Timer Control Register (WDTC: 0x9f)
//----------------------------------------------------------------------------------
//Location | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
//----------------------------------------------------------------------------------
// 0x9f | WDTE | 0 | CLEAR | 0 | 0 | PS2 | PS1 | PS0 |
//----------------------------------------------------------------------------------
// 复位值 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
//----------------------------------------------------------------------------------
//----------------------------------------------------------------------------------
// PS[2:0]| 111 | 110 | 101 | 100 | 011 | 010 | 001 | 000 |
//----------------------------------------------------------------------------------
// 分频数 | 1024 | 512 | 256 | 128 | 64 | 32 | 16 | 8 |
//-----------------------------------------------------------------------------------
// 晶振11.0592M 时钟周期单位：ms
//----------------------------------------------------------------------------------
// 时钟周期| 6068 | 3034 | 1517 | 758 | 379 | 190 | 94 | 47 |
//----------------------------------------------------------------------------------
//WDTE: 看门狗定时器使能位
//PS2~PS0: 时钟源分频选择位
sfr WDTC = 0x9F;
sbit WDTC_CLR = 0xa4; //WDTC^5; //设置1,看门狗计数器清0，同时该位变为0
sbit WDTE = 0xa6; //WDTC^7; //设置1,启动看门狗
//内部存储器页选择寄存器 (IMPSR: 0x85)
//----------------------------------------------------------------------------------
//Location | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
//----------------------------------------------------------------------------------
// 0x85 | 0 | 0 | 0 | 0 | 0 | 0 | PS1 | PS0 |
//----------------------------------------------------------------------------------
// 复位值 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
//----------------------------------------------------------------------------------
//----------------------------------------------------------------------------------
// PS[1:0]| 11 | 10 | 01 | 00 |
//----------------------------------------------------------------------------------
// 复位值 | 0xXY00 -- 0xXYFF| 0x0200 -- 0x02ff| 0x0100 -- 0x01ff| 0x0000 -- 0x00ff|
//----------------------------------------------------------------------------------
sfr IMPSR = 0x85;
//Watchdog KEY Control Register (WDTKEY: 0x97)
//----------------------------------------------------------------------------------
//Location | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
//----------------------------------------------------------------------------------
// 0x97 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
//----------------------------------------------------------------------------------
//需要修改WDTC内容是需写0x1e,0xe1到WDTKEY内，如要保护WDTC内容时写0xe1,0x1e,WDTC将无法改写
sfr WDTKEY = 0x97;
#endif
#ifdef sst89e554
/* Special SST89E554 Reg */
sfr AUXR = 0x8E;
//Watchdog Timer Data/Reload Register (WDTD)
//----------------------------------------------------------------------------------
//Location | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
//----------------------------------------------------------------------------------
// 0x85 | Watchdog Timer Data/Reload |
//----------------------------------------------------------------------------------
sfr WDTD = 0x85;
//Watchdog Timer Control Register (WDTC)
//----------------------------------------------------------------------------------
//Location | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
//----------------------------------------------------------------------------------
// 0xc0 | - | - | - | WDOUT | WDRE | WDTS | WDT | SWDT |
//----------------------------------------------------------------------------------
sfr WDTC = 0xc0;
// WDOUT: Watchdog output enale
// 0: Watchdog reset will not be export on Reset pin.
// 1: Watchdog reset if enable by WDRE, will assert Reset pin for 32 clocks.
sbit WDOUT = WDTC^4;
// WDRE: Watchdog timer reset enable.
// 0:Disable watchdog timer reset.
// 1:Enable watchdog timer reset.
sbit WDRE = WDTC^3;
// WDRS: Watchdog timer reset flag.
// 0:External hardware reset clears ther flag.
// Flag can also be cleared by writing a 1.
// Flag survives if chip reset happened because of watchdog timer overflow.
// 1:Hardware sets ther flag on watchdog overflow.
sbit WDRS = WDTC^2;
// WDT: Watchdog timer refresh.
// 0:Hardware resets ther bit when refresh is done.
// 1:Softwre sets ther bit to force a watchdog timer refresh.
sbit WDT = WDTC^1;
// SWDT: Start watchdog timer.
// 0:Stop WDT.
// 1:Start WDT.
sbit SWDT = WDTC^0;
#endif
//sbit SMOD = PCON^7;
sbit SMOD = 0x8e;
sbit P1_0 = P1^0;
sbit P1_1 = P1^1;
sbit P1_2 = P1^2;
sbit P1_3 = P1^3;
sbit P1_4 = P1^4;
sbit P1_5 = P1^5;
sbit P1_6 = P1^6;
sbit P1_7 = P1^7;
/* 8052 Extensions */
sfr T2CON = 0xC8;
sfr RCAP2L = 0xCA;
sfr RCAP2H = 0xCB;
sfr TL2 = 0xCC;
sfr TH2 = 0xCD;
/* BIT Registers */
/* PSW */
sbit CY = 0xD7;
sbit AC = 0xD6;
sbit F0 = 0xD5;
sbit RS1 = 0xD4;
sbit RS0 = 0xD3;
sbit OV = 0xD2;
sbit P = 0xD0;
/* TCON */
sbit TF1 = 0x8F;
sbit TR1 = 0x8E;
sbit TF0 = 0x8D;
sbit TR0 = 0x8C;
sbit IE1 = 0x8B;
sbit IT1 = 0x8A;
sbit IE0 = 0x89;
sbit IT0 = 0x88;
/* IE */
sbit EA = 0xAF;
sbit ES = 0xAC;
sbit ET1 = 0xAB;
sbit EX1 = 0xAA;
sbit ET0 = 0xA9;
sbit EX0 = 0xA8;
/* IP */
sbit PS = 0xBC;
sbit PT1 = 0xBB;
sbit PX1 = 0xBA;
sbit PT0 = 0xB9;
sbit PX0 = 0xB8;
/* P3 */
sbit RD = 0xB7;
sbit WR = 0xB6;
sbit T1 = 0xB5;
sbit T0 = 0xB4;
sbit INT1 = 0xB3;
sbit INT0 = 0xB2;
sbit TXD = 0xB1;
sbit RXD = 0xB0;
/* SCON */
sbit SM0 = 0x9F;
sbit SM1 = 0x9E;
sbit SM2 = 0x9D;
sbit REN = 0x9C;
sbit TB8 = 0x9B;
sbit RB8 = 0x9A;
sbit TI = 0x99;
sbit RI = 0x98;
/* 8052 Extensions */
/* IE */
sbit ET2 = 0xAD;
/* IP */
sbit PT2 = 0xBD;
/* P1 */
sbit T2EX = 0x91;
sbit T2 = 0x90;
/* T2CON */
sbit TF2 = 0xCF;
sbit T2IP = 0xCE;
sbit T2IE = 0xCD;
sbit T2RSE = 0xCC;
sbit BGEN = 0xCB;
sbit TR2 = 0xCA;
sbit C_T2 = 0xC9;
sbit CP_RL2= 0xC8;
sbit EX2 = 0xE8;
sbit EX3 = 0xE9;
sbit EX4 = 0xEA;
sbit EX5 = 0xEB;
sbit EWDI = 0xEC;
/*------------------------------------------------
Interrupt Vectors:
Interrupt Address = (Number * 8) + 3
------------------------------------------------*/
#define IE0_VECTOR 0 /* 0x03 External Interrupt 0 */
#define TF0_VECTOR 1 /* 0x0B Timer 0 */
#define IE1_VECTOR 2 /* 0x13 External Interrupt 1 */
#define TF1_VECTOR 3 /* 0x1B Timer 1 */
#define SIO_VECTOR 4 /* 0x23 Serial port */
#define TF2_VECTOR 5 /* 0X2B Timer 2 */
/*------------------------------------------------
------------------------------------------------*/
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