exp4.rpt

单片机外部中断和定时的c源码和cpld开发

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Device-Specific Information:                         d:\5_9\exp4\cpld\exp4.rpt
exp4

** EQUATIONS **

DPJTXD   : INPUT;
KRST     : INPUT;
PB0      : INPUT;
PB1      : INPUT;
PB2      : INPUT;
PB3      : INPUT;
PB4      : INPUT;
PB5      : INPUT;
PB6      : INPUT;
PB7      : INPUT;
PCTXD    : INPUT;
PD4      : INPUT;
START    : INPUT;

-- Node name is 'DPJRXD' 
-- Equation name is 'DPJRXD', type is output 
DPJRXD   =  _LC2_E25;

-- Node name is 'DPJRXD~1' 
-- Equation name is 'DPJRXD~1', location is LC2_E25, type is buried.
-- synthesized logic cell 
_LC2_E25 = LCELL( PCTXD);

-- Node name is 'DRST' 
-- Equation name is 'DRST', type is output 
DRST     =  _LC5_I48;

-- Node name is 'DRST~1' 
-- Equation name is 'DRST~1', location is LC5_I48, type is buried.
-- synthesized logic cell 
_LC5_I48 = LCELL( KRST);

-- Node name is 'LEDB0~1' 
-- Equation name is 'LEDB0~1', location is LC8_B32, type is buried.
-- synthesized logic cell 
_LC8_B32 = LCELL( PB0);

-- Node name is 'LEDB0' 
-- Equation name is 'LEDB0', type is output 
LEDB0    =  _LC8_B32;

-- Node name is 'LEDB1~1' 
-- Equation name is 'LEDB1~1', location is LC6_B6, type is buried.
-- synthesized logic cell 
_LC6_B6  = LCELL( PB1);

-- Node name is 'LEDB1' 
-- Equation name is 'LEDB1', type is output 
LEDB1    =  _LC6_B6;

-- Node name is 'LEDB2~1' 
-- Equation name is 'LEDB2~1', location is LC4_B9, type is buried.
-- synthesized logic cell 
_LC4_B9  = LCELL( PB2);

-- Node name is 'LEDB2' 
-- Equation name is 'LEDB2', type is output 
LEDB2    =  _LC4_B9;

-- Node name is 'LEDB3~1' 
-- Equation name is 'LEDB3~1', location is LC1_B29, type is buried.
-- synthesized logic cell 
_LC1_B29 = LCELL( PB3);

-- Node name is 'LEDB3' 
-- Equation name is 'LEDB3', type is output 
LEDB3    =  _LC1_B29;

-- Node name is 'LEDB4~1' 
-- Equation name is 'LEDB4~1', location is LC5_A50, type is buried.
-- synthesized logic cell 
_LC5_A50 = LCELL( PB4);

-- Node name is 'LEDB4' 
-- Equation name is 'LEDB4', type is output 
LEDB4    =  _LC5_A50;

-- Node name is 'LEDB5~1' 
-- Equation name is 'LEDB5~1', location is LC4_A42, type is buried.
-- synthesized logic cell 
_LC4_A42 = LCELL( PB5);

-- Node name is 'LEDB5' 
-- Equation name is 'LEDB5', type is output 
LEDB5    =  _LC4_A42;

-- Node name is 'LEDB6~1' 
-- Equation name is 'LEDB6~1', location is LC2_A40, type is buried.
-- synthesized logic cell 
_LC2_A40 = LCELL( PB6);

-- Node name is 'LEDB6' 
-- Equation name is 'LEDB6', type is output 
LEDB6    =  _LC2_A40;

-- Node name is 'LEDB7~1' 
-- Equation name is 'LEDB7~1', location is LC4_H10, type is buried.
-- synthesized logic cell 
_LC4_H10 = LCELL( PB7);

-- Node name is 'LEDB7' 
-- Equation name is 'LEDB7', type is output 
LEDB7    =  _LC4_H10;

-- Node name is 'PCRXD' 
-- Equation name is 'PCRXD', type is output 
PCRXD    =  _LC1_J14;

-- Node name is 'PCRXD~1' 
-- Equation name is 'PCRXD~1', location is LC1_J14, type is buried.
-- synthesized logic cell 
_LC1_J14 = LCELL( DPJTXD);

-- Node name is 'PD2~1' 
-- Equation name is 'PD2~1', location is LC2_B23, type is buried.
-- synthesized logic cell 
_LC2_B23 = LCELL( START);

-- Node name is 'PD2' 
-- Equation name is 'PD2', type is output 
PD2      = !_LC2_B23;

-- Node name is 'PD5~1' 
-- Equation name is 'PD5~1', location is LC1_G18, type is buried.
-- synthesized logic cell 
_LC1_G18 = LCELL( PD4);

-- Node name is 'PD5' 
-- Equation name is 'PD5', type is output 
PD5      =  _LC1_G18;



Project Information                                  d:\5_9\exp4\cpld\exp4.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:07
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:02
   --------------------------             --------
   Total Time                             00:00:10


Memory Allocated
-----------------

Peak memory allocated during compilation  = 49,195K