key.rpt

4*4键盘程序c源码以及在cpld环境下的运行

-- Equation name is 'LED13~1', location is LC4_D34, type is buried.
-- synthesized logic cell 
_LC4_D34 = LCELL( P13);

-- Node name is 'LED13' 
-- Equation name is 'LED13', type is output 
LED13    =  _LC4_D34;

-- Node name is 'LED14~1' 
-- Equation name is 'LED14~1', location is LC2_A28, type is buried.
-- synthesized logic cell 
_LC2_A28 = LCELL( P14);

-- Node name is 'LED14' 
-- Equation name is 'LED14', type is output 
LED14    =  _LC2_A28;

-- Node name is 'LED15~1' 
-- Equation name is 'LED15~1', location is LC7_F31, type is buried.
-- synthesized logic cell 
_LC7_F31 = LCELL( P15);

-- Node name is 'LED15' 
-- Equation name is 'LED15', type is output 
LED15    =  _LC7_F31;

-- Node name is 'LED16~1' 
-- Equation name is 'LED16~1', location is LC2_A45, type is buried.
-- synthesized logic cell 
_LC2_A45 = LCELL( P16);

-- Node name is 'LED16' 
-- Equation name is 'LED16', type is output 
LED16    =  _LC2_A45;

-- Node name is 'LED17~1' 
-- Equation name is 'LED17~1', location is LC1_E6, type is buried.
-- synthesized logic cell 
_LC1_E6  = LCELL( P17);

-- Node name is 'LED17' 
-- Equation name is 'LED17', type is output 
LED17    =  _LC1_E6;

-- Node name is 'LED20~1' 
-- Equation name is 'LED20~1', location is LC6_B26, type is buried.
-- synthesized logic cell 
_LC6_B26 = LCELL( P20);

-- Node name is 'LED20' 
-- Equation name is 'LED20', type is output 
LED20    =  _LC6_B26;

-- Node name is 'LED21~1' 
-- Equation name is 'LED21~1', location is LC7_D8, type is buried.
-- synthesized logic cell 
_LC7_D8  = LCELL( P21);

-- Node name is 'LED21' 
-- Equation name is 'LED21', type is output 
LED21    =  _LC7_D8;

-- Node name is 'LED22~1' 
-- Equation name is 'LED22~1', location is LC8_H24, type is buried.
-- synthesized logic cell 
_LC8_H24 = LCELL( P22);

-- Node name is 'LED22' 
-- Equation name is 'LED22', type is output 
LED22    =  _LC8_H24;

-- Node name is 'LED23~1' 
-- Equation name is 'LED23~1', location is LC1_G25, type is buried.
-- synthesized logic cell 
_LC1_G25 = LCELL( P23);

-- Node name is 'LED23' 
-- Equation name is 'LED23', type is output 
LED23    =  _LC1_G25;

-- Node name is 'LED24~1' 
-- Equation name is 'LED24~1', location is LC1_K21, type is buried.
-- synthesized logic cell 
_LC1_K21 = LCELL( P24);

-- Node name is 'LED24' 
-- Equation name is 'LED24', type is output 
LED24    =  _LC1_K21;

-- Node name is 'LED25~1' 
-- Equation name is 'LED25~1', location is LC2_H27, type is buried.
-- synthesized logic cell 
_LC2_H27 = LCELL( P25);

-- Node name is 'LED25' 
-- Equation name is 'LED25', type is output 
LED25    =  _LC2_H27;

-- Node name is 'LED26~1' 
-- Equation name is 'LED26~1', location is LC4_B25, type is buried.
-- synthesized logic cell 
_LC4_B25 = LCELL( P26);

-- Node name is 'LED26' 
-- Equation name is 'LED26', type is output 
LED26    =  _LC4_B25;

-- Node name is 'LED27~1' 
-- Equation name is 'LED27~1', location is LC4_G46, type is buried.
-- synthesized logic cell 
_LC4_G46 = LCELL( P27);

-- Node name is 'LED27' 
-- Equation name is 'LED27', type is output 
LED27    =  _LC4_G46;

-- Node name is 'PCRXD' 
-- Equation name is 'PCRXD', type is output 
PCRXD    =  _LC4_G13;

-- Node name is 'PCRXD~1' 
-- Equation name is 'PCRXD~1', location is LC4_G13, type is buried.
-- synthesized logic cell 
_LC4_G13 = LCELL( DPJTXD);

-- Node name is 'p30~1' 
-- Equation name is 'p30~1', location is LC5_C21, type is buried.
-- synthesized logic cell 
_LC5_C21 = LCELL( key0);

-- Node name is 'p30' 
-- Equation name is 'p30', type is output 
p30      =  _LC5_C21;

-- Node name is 'p31~1' 
-- Equation name is 'p31~1', location is LC5_A18, type is buried.
-- synthesized logic cell 
_LC5_A18 = LCELL( key1);

-- Node name is 'p31' 
-- Equation name is 'p31', type is output 
p31      =  _LC5_A18;

-- Node name is 'p32~1' 
-- Equation name is 'p32~1', location is LC1_H11, type is buried.
-- synthesized logic cell 
_LC1_H11 = LCELL( key2);

-- Node name is 'p32' 
-- Equation name is 'p32', type is output 
p32      =  _LC1_H11;

-- Node name is 'p33~1' 
-- Equation name is 'p33~1', location is LC4_L3, type is buried.
-- synthesized logic cell 
_LC4_L3  = LCELL( key3);

-- Node name is 'p33' 
-- Equation name is 'p33', type is output 
p33      =  _LC4_L3;

-- Node name is 'p34~1' 
-- Equation name is 'p34~1', location is LC8_F24, type is buried.
-- synthesized logic cell 
_LC8_F24 = LCELL( key4);

-- Node name is 'p34' 
-- Equation name is 'p34', type is output 
p34      =  _LC8_F24;

-- Node name is 'p35~1' 
-- Equation name is 'p35~1', location is LC7_J27, type is buried.
-- synthesized logic cell 
_LC7_J27 = LCELL( key5);

-- Node name is 'p35' 
-- Equation name is 'p35', type is output 
p35      =  _LC7_J27;

-- Node name is 'p36~1' 
-- Equation name is 'p36~1', location is LC8_B2, type is buried.
-- synthesized logic cell 
_LC8_B2  = LCELL( key6);

-- Node name is 'p36' 
-- Equation name is 'p36', type is output 
p36      =  _LC8_B2;

-- Node name is 'p37~1' 
-- Equation name is 'p37~1', location is LC5_I43, type is buried.
-- synthesized logic cell 
_LC5_I43 = LCELL( key7);

-- Node name is 'p37' 
-- Equation name is 'p37', type is output 
p37      =  _LC5_I43;



Project Information                           e:\keil\keyvalue\keycpld\key.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:04
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:06


Memory Allocated
-----------------

Peak memory allocated during compilation  = 48,886K