📄 key.rpt
字号:
182 - - - -- INPUT ^ 0 0 0 1 PCTXD
78 - - - -- INPUT ^ 0 0 0 1 P10
80 - - - -- INPUT ^ 0 0 0 1 P11
184 - - - -- INPUT ^ 0 0 0 1 P12
79 - - - -- INPUT ^ 0 0 0 1 P13
183 - - - -- INPUT ^ 0 0 0 1 P14
125 - - F -- INPUT ^ 0 0 0 1 P15
7 - - A -- INPUT ^ 0 0 0 1 P16
131 - - E -- INPUT ^ 0 0 0 1 P17
12 - - B -- INPUT ^ 0 0 0 1 P20
135 - - D -- INPUT ^ 0 0 0 1 P21
36 - - H -- INPUT ^ 0 0 0 1 P22
29 - - G -- INPUT ^ 0 0 0 1 P23
113 - - K -- INPUT ^ 0 0 0 1 P24
30 - - H -- INPUT ^ 0 0 0 1 P25
147 - - B -- INPUT ^ 0 0 0 1 P26
121 - - G -- INPUT ^ 0 0 0 1 P27
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\keil\keyvalue\keycpld\key.rpt
key
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
83 - - - 25 OUTPUT 0 1 0 0 DPJRXD
18 - - D -- OUTPUT 0 1 0 0 DRST
41 - - K -- OUTPUT 0 1 0 0 LED10
14 - - C -- OUTPUT 0 1 0 0 LED11
13 - - B -- OUTPUT 0 1 0 0 LED12
17 - - D -- OUTPUT 0 1 0 0 LED13
10 - - A -- OUTPUT 0 1 0 0 LED14
27 - - F -- OUTPUT 0 1 0 0 LED15
8 - - A -- OUTPUT 0 1 0 0 LED16
132 - - E -- OUTPUT 0 1 0 0 LED17
143 - - B -- OUTPUT 0 1 0 0 LED20
133 - - D -- OUTPUT 0 1 0 0 LED21
119 - - H -- OUTPUT 0 1 0 0 LED22
122 - - G -- OUTPUT 0 1 0 0 LED23
114 - - K -- OUTPUT 0 1 0 0 LED24
187 - - - 28 OUTPUT 0 1 0 0 LED25
144 - - B -- OUTPUT 0 1 0 0 LED26
28 - - G -- OUTPUT 0 1 0 0 LED27
93 - - - 14 OUTPUT 0 1 0 0 PCRXD
139 - - C -- OUTPUT 0 1 0 0 p30
148 - - A -- OUTPUT 0 1 0 0 p31
120 - - H -- OUTPUT 0 1 0 0 p32
112 - - L -- OUTPUT 0 1 0 0 p33
126 - - F -- OUTPUT 0 1 0 0 p34
40 - - J -- OUTPUT 0 1 0 0 p35
142 - - B -- OUTPUT 0 1 0 0 p36
38 - - I -- OUTPUT 0 1 0 0 p37
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\keil\keyvalue\keycpld\key.rpt
key
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - K 26 LCELL s 1 0 1 0 DPJRXD~1
- 5 - I 34 LCELL s 1 0 1 0 DRST~1
- 8 - K 30 LCELL s 1 0 1 0 LED10~1
- 2 - C 44 LCELL s 1 0 1 0 LED11~1
- 8 - B 37 LCELL s 1 0 1 0 LED12~1
- 4 - D 34 LCELL s 1 0 1 0 LED13~1
- 2 - A 28 LCELL s 1 0 1 0 LED14~1
- 7 - F 31 LCELL s 1 0 1 0 LED15~1
- 2 - A 45 LCELL s 1 0 1 0 LED16~1
- 1 - E 06 LCELL s 1 0 1 0 LED17~1
- 6 - B 26 LCELL s 1 0 1 0 LED20~1
- 7 - D 08 LCELL s 1 0 1 0 LED21~1
- 8 - H 24 LCELL s 1 0 1 0 LED22~1
- 1 - G 25 LCELL s 1 0 1 0 LED23~1
- 1 - K 21 LCELL s 1 0 1 0 LED24~1
- 2 - H 27 LCELL s 1 0 1 0 LED25~1
- 4 - B 25 LCELL s 1 0 1 0 LED26~1
- 4 - G 46 LCELL s 1 0 1 0 LED27~1
- 4 - G 13 LCELL s 1 0 1 0 PCRXD~1
- 5 - C 21 LCELL s 1 0 1 0 p30~1
- 5 - A 18 LCELL s 1 0 1 0 p31~1
- 1 - H 11 LCELL s 1 0 1 0 p32~1
- 4 - L 03 LCELL s 1 0 1 0 p33~1
- 8 - F 24 LCELL s 1 0 1 0 p34~1
- 7 - J 27 LCELL s 1 0 1 0 p35~1
- 8 - B 02 LCELL s 1 0 1 0 p36~1
- 5 - I 43 LCELL s 1 0 1 0 p37~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\keil\keyvalue\keycpld\key.rpt
key
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 3/208( 1%) 1/104( 0%) 1/104( 0%) 2/16( 12%) 3/16( 18%) 0/16( 0%)
B: 4/208( 1%) 2/104( 1%) 1/104( 0%) 3/16( 18%) 4/16( 25%) 0/16( 0%)
C: 1/208( 0%) 1/104( 0%) 1/104( 0%) 1/16( 6%) 2/16( 12%) 0/16( 0%)
D: 1/208( 0%) 1/104( 0%) 2/104( 1%) 1/16( 6%) 3/16( 18%) 0/16( 0%)
E: 1/208( 0%) 1/104( 0%) 0/104( 0%) 1/16( 6%) 1/16( 6%) 0/16( 0%)
F: 3/208( 1%) 1/104( 0%) 0/104( 0%) 2/16( 12%) 2/16( 12%) 0/16( 0%)
G: 2/208( 0%) 2/104( 1%) 1/104( 0%) 2/16( 12%) 2/16( 12%) 0/16( 0%)
H: 3/208( 1%) 2/104( 1%) 0/104( 0%) 3/16( 18%) 2/16( 12%) 0/16( 0%)
I: 1/208( 0%) 0/104( 0%) 2/104( 1%) 1/16( 6%) 1/16( 6%) 0/16( 0%)
J: 2/208( 0%) 0/104( 0%) 0/104( 0%) 1/16( 6%) 1/16( 6%) 0/16( 0%)
K: 2/208( 0%) 1/104( 0%) 0/104( 0%) 1/16( 6%) 2/16( 12%) 0/16( 0%)
L: 1/208( 0%) 1/104( 0%) 0/104( 0%) 1/16( 6%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
25: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
37: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
38: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
39: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
40: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
41: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
42: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
43: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
44: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
45: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
46: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
47: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
48: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
49: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
50: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
51: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
52: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\keil\keyvalue\keycpld\key.rpt
key
** EQUATIONS **
DPJTXD : INPUT;
key0 : INPUT;
key1 : INPUT;
key2 : INPUT;
key3 : INPUT;
key4 : INPUT;
key5 : INPUT;
key6 : INPUT;
key7 : INPUT;
KRST : INPUT;
PCTXD : INPUT;
P10 : INPUT;
P11 : INPUT;
P12 : INPUT;
P13 : INPUT;
P14 : INPUT;
P15 : INPUT;
P16 : INPUT;
P17 : INPUT;
P20 : INPUT;
P21 : INPUT;
P22 : INPUT;
P23 : INPUT;
P24 : INPUT;
P25 : INPUT;
P26 : INPUT;
P27 : INPUT;
-- Node name is 'DPJRXD'
-- Equation name is 'DPJRXD', type is output
DPJRXD = _LC1_K26;
-- Node name is 'DPJRXD~1'
-- Equation name is 'DPJRXD~1', location is LC1_K26, type is buried.
-- synthesized logic cell
_LC1_K26 = LCELL( PCTXD);
-- Node name is 'DRST'
-- Equation name is 'DRST', type is output
DRST = _LC5_I34;
-- Node name is 'DRST~1'
-- Equation name is 'DRST~1', location is LC5_I34, type is buried.
-- synthesized logic cell
_LC5_I34 = LCELL( KRST);
-- Node name is 'LED10~1'
-- Equation name is 'LED10~1', location is LC8_K30, type is buried.
-- synthesized logic cell
_LC8_K30 = LCELL( P10);
-- Node name is 'LED10'
-- Equation name is 'LED10', type is output
LED10 = _LC8_K30;
-- Node name is 'LED11~1'
-- Equation name is 'LED11~1', location is LC2_C44, type is buried.
-- synthesized logic cell
_LC2_C44 = LCELL( P11);
-- Node name is 'LED11'
-- Equation name is 'LED11', type is output
LED11 = _LC2_C44;
-- Node name is 'LED12~1'
-- Equation name is 'LED12~1', location is LC8_B37, type is buried.
-- synthesized logic cell
_LC8_B37 = LCELL( P12);
-- Node name is 'LED12'
-- Equation name is 'LED12', type is output
LED12 = _LC8_B37;
-- Node name is 'LED13~1'
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