key1.rpt

4*4键盘程序c源码以及在cpld环境下的运行

-- synthesized logic cell 
_LC5_L7  = LCELL( P22);

-- Node name is 'LED22' 
-- Equation name is 'LED22', type is output 
LED22    =  _LC5_L7;

-- Node name is 'LED23~1' 
-- Equation name is 'LED23~1', location is LC4_L4, type is buried.
-- synthesized logic cell 
_LC4_L4  = LCELL( P23);

-- Node name is 'LED23' 
-- Equation name is 'LED23', type is output 
LED23    =  _LC4_L4;

-- Node name is 'LED24~1' 
-- Equation name is 'LED24~1', location is LC5_K41, type is buried.
-- synthesized logic cell 
_LC5_K41 = LCELL( P24);

-- Node name is 'LED24' 
-- Equation name is 'LED24', type is output 
LED24    =  _LC5_K41;

-- Node name is 'LED25~1' 
-- Equation name is 'LED25~1', location is LC1_K38, type is buried.
-- synthesized logic cell 
_LC1_K38 = LCELL( P25);

-- Node name is 'LED25' 
-- Equation name is 'LED25', type is output 
LED25    =  _LC1_K38;

-- Node name is 'LED26~1' 
-- Equation name is 'LED26~1', location is LC5_J31, type is buried.
-- synthesized logic cell 
_LC5_J31 = LCELL( P26);

-- Node name is 'LED26' 
-- Equation name is 'LED26', type is output 
LED26    =  _LC5_J31;

-- Node name is 'LED27~1' 
-- Equation name is 'LED27~1', location is LC5_I23, type is buried.
-- synthesized logic cell 
_LC5_I23 = LCELL( P27);

-- Node name is 'LED27' 
-- Equation name is 'LED27', type is output 
LED27    =  _LC5_I23;

-- Node name is 'PCRXD' 
-- Equation name is 'PCRXD', type is output 
PCRXD    =  _LC4_G13;

-- Node name is 'PCRXD~1' 
-- Equation name is 'PCRXD~1', location is LC4_G13, type is buried.
-- synthesized logic cell 
_LC4_G13 = LCELL( DPJTXD);

-- Node name is 'p30~1' 
-- Equation name is 'p30~1', location is LC8_H49, type is buried.
-- synthesized logic cell 
_LC8_H49 = LCELL( key0);

-- Node name is 'p30' 
-- Equation name is 'p30', type is output 
p30      =  _LC8_H49;

-- Node name is 'p31~1' 
-- Equation name is 'p31~1', location is LC3_G27, type is buried.
-- synthesized logic cell 
_LC3_G27 = LCELL( key1);

-- Node name is 'p31' 
-- Equation name is 'p31', type is output 
p31      =  _LC3_G27;

-- Node name is 'p32~1' 
-- Equation name is 'p32~1', location is LC8_G50, type is buried.
-- synthesized logic cell 
_LC8_G50 = LCELL( key2);

-- Node name is 'p32' 
-- Equation name is 'p32', type is output 
p32      =  _LC8_G50;

-- Node name is 'p33~1' 
-- Equation name is 'p33~1', location is LC8_F40, type is buried.
-- synthesized logic cell 
_LC8_F40 = LCELL( key3);

-- Node name is 'p33' 
-- Equation name is 'p33', type is output 
p33      =  _LC8_F40;

-- Node name is 'p34~1' 
-- Equation name is 'p34~1', location is LC2_F51, type is buried.
-- synthesized logic cell 
_LC2_F51 = LCELL( key4);

-- Node name is 'p34' 
-- Equation name is 'p34', type is output 
p34      =  _LC2_F51;

-- Node name is 'p35~1' 
-- Equation name is 'p35~1', location is LC1_F52, type is buried.
-- synthesized logic cell 
_LC1_F52 = LCELL( key5);

-- Node name is 'p35' 
-- Equation name is 'p35', type is output 
p35      =  _LC1_F52;

-- Node name is 'p36~1' 
-- Equation name is 'p36~1', location is LC5_E47, type is buried.
-- synthesized logic cell 
_LC5_E47 = LCELL( key6);

-- Node name is 'p36' 
-- Equation name is 'p36', type is output 
p36      =  _LC5_E47;

-- Node name is 'p37~1' 
-- Equation name is 'p37~1', location is LC1_E46, type is buried.
-- synthesized logic cell 
_LC1_E46 = LCELL( key7);

-- Node name is 'p37' 
-- Equation name is 'p37', type is output 
p37      =  _LC1_E46;



Project Information                                  d:\keyvalue\cpld\key1.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:08
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:02
   --------------------------             --------
   Total Time                             00:00:10


Memory Allocated
-----------------

Peak memory allocated during compilation  = 51,376K