📄 key1.rpt
字号:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\keyvalue\cpld\key1.rpt
key1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 1/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 4/208( 1%) 0/104( 0%) 0/104( 0%) 2/16( 12%) 0/16( 0%) 0/16( 0%)
F: 4/208( 1%) 0/104( 0%) 0/104( 0%) 3/16( 18%) 0/16( 0%) 0/16( 0%)
G: 3/208( 1%) 1/104( 0%) 0/104( 0%) 2/16( 12%) 0/16( 0%) 0/16( 0%)
H: 2/208( 0%) 0/104( 0%) 0/104( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
I: 1/208( 0%) 1/104( 0%) 0/104( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
J: 2/208( 0%) 0/104( 0%) 1/104( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
K: 3/208( 1%) 0/104( 0%) 3/104( 2%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
L: 4/208( 1%) 2/104( 1%) 3/104( 2%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
25: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
28: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
29: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
30: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
31: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
32: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
33: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
34: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
35: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
36: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
37: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
38: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
39: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
40: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
41: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
42: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
43: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
44: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
45: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
46: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
47: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
48: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
49: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
50: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
51: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
52: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\keyvalue\cpld\key1.rpt
key1
** EQUATIONS **
DPJTXD : INPUT;
key0 : INPUT;
key1 : INPUT;
key2 : INPUT;
key3 : INPUT;
key4 : INPUT;
key5 : INPUT;
key6 : INPUT;
key7 : INPUT;
PCTXD : INPUT;
P10 : INPUT;
P11 : INPUT;
P12 : INPUT;
P13 : INPUT;
P14 : INPUT;
P15 : INPUT;
P16 : INPUT;
P17 : INPUT;
P20 : INPUT;
P21 : INPUT;
P22 : INPUT;
P23 : INPUT;
P24 : INPUT;
P25 : INPUT;
P26 : INPUT;
P27 : INPUT;
-- Node name is 'DPJRXD'
-- Equation name is 'DPJRXD', type is output
DPJRXD = _LC1_L26;
-- Node name is 'DPJRXD~1'
-- Equation name is 'DPJRXD~1', location is LC1_L26, type is buried.
-- synthesized logic cell
_LC1_L26 = LCELL( PCTXD);
-- Node name is 'LED10~1'
-- Equation name is 'LED10~1', location is LC1_F13, type is buried.
-- synthesized logic cell
_LC1_F13 = LCELL( P10);
-- Node name is 'LED10'
-- Equation name is 'LED10', type is output
LED10 = _LC1_F13;
-- Node name is 'LED11~1'
-- Equation name is 'LED11~1', location is LC1_E9, type is buried.
-- synthesized logic cell
_LC1_E9 = LCELL( P11);
-- Node name is 'LED11'
-- Equation name is 'LED11', type is output
LED11 = _LC1_E9;
-- Node name is 'LED12~1'
-- Equation name is 'LED12~1', location is LC4_E7, type is buried.
-- synthesized logic cell
_LC4_E7 = LCELL( P12);
-- Node name is 'LED12'
-- Equation name is 'LED12', type is output
LED12 = _LC4_E7;
-- Node name is 'LED13~1'
-- Equation name is 'LED13~1', location is LC1_C7, type is buried.
-- synthesized logic cell
_LC1_C7 = LCELL( P13);
-- Node name is 'LED13'
-- Equation name is 'LED13', type is output
LED13 = _LC1_C7;
-- Node name is 'LED14~1'
-- Equation name is 'LED14~1', location is LC4_K5, type is buried.
-- synthesized logic cell
_LC4_K5 = LCELL( P14);
-- Node name is 'LED14'
-- Equation name is 'LED14', type is output
LED14 = _LC4_K5;
-- Node name is 'LED15~1'
-- Equation name is 'LED15~1', location is LC1_J5, type is buried.
-- synthesized logic cell
_LC1_J5 = LCELL( P15);
-- Node name is 'LED15'
-- Equation name is 'LED15', type is output
LED15 = _LC1_J5;
-- Node name is 'LED16~1'
-- Equation name is 'LED16~1', location is LC4_G3, type is buried.
-- synthesized logic cell
_LC4_G3 = LCELL( P16);
-- Node name is 'LED16'
-- Equation name is 'LED16', type is output
LED16 = _LC4_G3;
-- Node name is 'LED17~1'
-- Equation name is 'LED17~1', location is LC7_L3, type is buried.
-- synthesized logic cell
_LC7_L3 = LCELL( P17);
-- Node name is 'LED17'
-- Equation name is 'LED17', type is output
LED17 = _LC7_L3;
-- Node name is 'LED20~1'
-- Equation name is 'LED20~1', location is LC2_H1, type is buried.
-- synthesized logic cell
_LC2_H1 = LCELL( P20);
-- Node name is 'LED20'
-- Equation name is 'LED20', type is output
LED20 = _LC2_H1;
-- Node name is 'LED21~1'
-- Equation name is 'LED21~1', location is LC4_L2, type is buried.
-- synthesized logic cell
_LC4_L2 = LCELL( P21);
-- Node name is 'LED21'
-- Equation name is 'LED21', type is output
LED21 = _LC4_L2;
-- Node name is 'LED22~1'
-- Equation name is 'LED22~1', location is LC5_L7, type is buried.
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