📄 key1.rpt
字号:
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: d:\keyvalue\cpld\key1.rpt
key1
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
C7 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/26( 3%)
E7 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/26( 3%)
E9 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/26( 3%)
E46 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/26( 3%)
E47 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/26( 3%)
F13 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/26( 3%)
F40 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/26( 3%)
F51 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/26( 3%)
F52 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/26( 3%)
G3 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/26( 3%)
G13 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/26( 3%)
G27 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/26( 3%)
G50 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/26( 3%)
H1 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/26( 3%)
H49 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/26( 3%)
I23 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/26( 3%)
J5 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/26( 3%)
J31 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/26( 3%)
K5 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/26( 3%)
K38 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/26( 3%)
K41 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/26( 3%)
L2 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/26( 3%)
L3 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/26( 3%)
L4 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/26( 3%)
L7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/26( 3%)
L26 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/26( 3%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 1/6 ( 16%)
Total I/O pins used: 51/141 ( 36%)
Total logic cells used: 26/4992 ( 0%)
Total embedded cells used: 0/192 ( 0%)
Total EABs used: 0/12 ( 0%)
Average fan-in: 1.00/4 ( 25%)
Total fan-in: 26/19968 ( 0%)
Total input pins required: 26
Total input I/O cell registers required: 0
Total output pins required: 26
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 26
Total flipflops required: 0
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 26/4992 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 EA 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 4/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 4/0
G: 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 4/0
H: 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2/0
I: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1/0
J: 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2/0
K: 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 3/0
L: 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5/0
Total: 1 1 2 1 2 0 3 0 1 0 0 0 2 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 1 0 1 1 0 0 0 0 1 1 0 1 1 1 1 26/0
Device-Specific Information: d:\keyvalue\cpld\key1.rpt
key1
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
85 - - - 24 INPUT ^ 0 0 0 1 DPJTXD
120 - - H -- INPUT ^ 0 0 0 1 key0
121 - - G -- INPUT ^ 0 0 0 1 key1
122 - - G -- INPUT ^ 0 0 0 1 key2
125 - - F -- INPUT ^ 0 0 0 1 key3
126 - - F -- INPUT ^ 0 0 0 1 key4
127 - - F -- INPUT ^ 0 0 0 1 key5
128 - - E -- INPUT ^ 0 0 0 1 key6
131 - - E -- INPUT ^ 0 0 0 1 key7
182 - - - -- INPUT ^ 0 0 0 1 PCTXD
57 - - - 43 INPUT ^ 0 0 0 1 P10
58 - - - 42 INPUT ^ 0 0 0 1 P11
60 - - - 40 INPUT ^ 0 0 0 1 P12
61 - - - 40 INPUT ^ 0 0 0 1 P13
62 - - - 36 INPUT ^ 0 0 0 1 P14
63 - - - 35 INPUT ^ 0 0 0 1 P15
64 - - - 35 INPUT ^ 0 0 0 1 P16
65 - - - 34 INPUT ^ 0 0 0 1 P17
75 - - - 27 INPUT ^ 0 0 0 1 P20
74 - - - 28 INPUT ^ 0 0 0 1 P21
73 - - - 29 INPUT ^ 0 0 0 1 P22
71 - - - 30 INPUT ^ 0 0 0 1 P23
70 - - - 31 INPUT ^ 0 0 0 1 P24
69 - - - 32 INPUT ^ 0 0 0 1 P25
68 - - - 33 INPUT ^ 0 0 0 1 P26
67 - - - 33 INPUT ^ 0 0 0 1 P27
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\keyvalue\cpld\key1.rpt
key1
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
83 - - - 25 OUTPUT 0 1 0 0 DPJRXD
94 - - - 13 OUTPUT 0 1 0 0 LED10
95 - - - 09 OUTPUT 0 1 0 0 LED11
96 - - - 08 OUTPUT 0 1 0 0 LED12
97 - - - 07 OUTPUT 0 1 0 0 LED13
99 - - - 06 OUTPUT 0 1 0 0 LED14
100 - - - 05 OUTPUT 0 1 0 0 LED15
101 - - - 04 OUTPUT 0 1 0 0 LED16
102 - - - 03 OUTPUT 0 1 0 0 LED17
103 - - - 02 OUTPUT 0 1 0 0 LED20
104 - - - 01 OUTPUT 0 1 0 0 LED21
111 - - L -- OUTPUT 0 1 0 0 LED22
112 - - L -- OUTPUT 0 1 0 0 LED23
113 - - K -- OUTPUT 0 1 0 0 LED24
114 - - K -- OUTPUT 0 1 0 0 LED25
115 - - J -- OUTPUT 0 1 0 0 LED26
116 - - I -- OUTPUT 0 1 0 0 LED27
93 - - - 14 OUTPUT 0 1 0 0 PCRXD
44 - - K -- OUTPUT 0 1 0 0 p30
45 - - L -- OUTPUT 0 1 0 0 p31
46 - - L -- OUTPUT 0 1 0 0 p32
47 - - L -- OUTPUT 0 1 0 0 p33
53 - - - 52 OUTPUT 0 1 0 0 p34
54 - - - 51 OUTPUT 0 1 0 0 p35
55 - - - 48 OUTPUT 0 1 0 0 p36
56 - - - 45 OUTPUT 0 1 0 0 p37
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\keyvalue\cpld\key1.rpt
key1
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - L 26 LCELL s 1 0 1 0 DPJRXD~1
- 1 - F 13 LCELL s 1 0 1 0 LED10~1
- 1 - E 09 LCELL s 1 0 1 0 LED11~1
- 4 - E 07 LCELL s 1 0 1 0 LED12~1
- 1 - C 07 LCELL s 1 0 1 0 LED13~1
- 4 - K 05 LCELL s 1 0 1 0 LED14~1
- 1 - J 05 LCELL s 1 0 1 0 LED15~1
- 4 - G 03 LCELL s 1 0 1 0 LED16~1
- 7 - L 03 LCELL s 1 0 1 0 LED17~1
- 2 - H 01 LCELL s 1 0 1 0 LED20~1
- 4 - L 02 LCELL s 1 0 1 0 LED21~1
- 5 - L 07 LCELL s 1 0 1 0 LED22~1
- 4 - L 04 LCELL s 1 0 1 0 LED23~1
- 5 - K 41 LCELL s 1 0 1 0 LED24~1
- 1 - K 38 LCELL s 1 0 1 0 LED25~1
- 5 - J 31 LCELL s 1 0 1 0 LED26~1
- 5 - I 23 LCELL s 1 0 1 0 LED27~1
- 4 - G 13 LCELL s 1 0 1 0 PCRXD~1
- 8 - H 49 LCELL s 1 0 1 0 p30~1
- 3 - G 27 LCELL s 1 0 1 0 p31~1
- 8 - G 50 LCELL s 1 0 1 0 p32~1
- 8 - F 40 LCELL s 1 0 1 0 p33~1
- 2 - F 51 LCELL s 1 0 1 0 p34~1
- 1 - F 52 LCELL s 1 0 1 0 p35~1
- 5 - E 47 LCELL s 1 0 1 0 p36~1
- 1 - E 46 LCELL s 1 0 1 0 p37~1
Code:
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