dpram_75p.tdf

来自「91c111芯片的网络模块的原理图以及和ep1c6fpga连线相关的例子程序」· TDF 代码 · 共 49 行

--altdpram DEVICE_FAMILY="Cyclone" lpm_hint="RAM_BLOCK_TYPE=AUTO" RDCONTROL_ACLR="OFF" RDCONTROL_REG="UNREGISTERED" SUPPRESS_MEMORY_CONVERSION_WARNINGS="ON" USE_EAB="ON" WIDTH=8 WIDTHAD=6 data inclock outclock outclocken q rdaddress wraddress wren RAM_BLOCK_TYPE="AUTO"
--VERSION_BEGIN 5.1 cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:11:08:14:10:50:SJ cbx_cycloneii 2005:12:13:10:36:54:SJ cbx_lpm_add_sub 2005:11:02:10:42:42:SJ cbx_lpm_compare 2005:07:11:09:41:28:SJ cbx_lpm_decode 2005:04:27:14:28:48:SJ cbx_lpm_mux 2005:12:13:16:24:06:SJ cbx_mgl 2006:01:12:16:15:18:SJ cbx_stratix 2005:12:28:11:18:26:SJ cbx_stratixii 2005:11:02:10:43:56:SJ cbx_util_mgl 2005:09:12:10:23:22:SJ  VERSION_END


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FUNCTION altsyncram_bhc1 (address_a[5..0], address_b[5..0], clock0, clock1, clocken1, data_a[7..0], wren_a)
RETURNS ( q_b[7..0]);

--synthesis_resources = M4K 8 
SUBDESIGN dpram_75p
( 
	data[7..0]	:	input;
	inclock	:	input;
	outclock	:	input;
	outclocken	:	input;
	q[7..0]	:	output;
	rdaddress[5..0]	:	input;
	wraddress[5..0]	:	input;
	wren	:	input;
) 
VARIABLE 
	altsyncram1 : altsyncram_bhc1;

BEGIN 
	altsyncram1.address_a[] = wraddress[];
	altsyncram1.address_b[] = rdaddress[];
	altsyncram1.clock0 = inclock;
	altsyncram1.clock1 = outclock;
	altsyncram1.clocken1 = outclocken;
	altsyncram1.data_a[] = data[];
	altsyncram1.wren_a = wren;
	q[] = altsyncram1.q_b[];
END;
--VALID FILE