net_1c6_911.fit.qmsg

来自「91c111芯片的网络模块的原理图以及和ep1c6fpga连线相关的例子程序」· QMSG 代码 · 共 50 行 · 第 1/5 页

{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_PLL_CLK_PROMOTION" "" "Info: Promoted PLL clock signals" { { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK_USER" "altpll0:inst1\|altpll:altpll_component\|_clk0 " "Info: Promoted signal \"altpll0:inst1\|altpll:altpll_component\|_clk0\" to use global clock (user assigned)" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "altpll0:inst1\|altpll:altpll_component\|_clk0" } { 0 "altpll0:inst1\|altpll:altpll_component\|_clk0" } } } } { "net_1c6_911.bdf" "" { Schematic "D:/Test/net_1c6_911/net_1c6_911.bdf" { { -216 64 304 -40 "inst1" "" } } } } { "altpll.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altpll.tdf" 765 3 0 } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "" { altpll0:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "D:/Test/net_1c6_911/net_1c6_911.fld" "" { Floorplan "D:/Test/net_1c6_911/net_1c6_911.fld" "" "" { altpll0:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock (user assigned)" 0 0} { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK_USER" "altpll0:inst1\|altpll:altpll_component\|_clk1 " "Info: Promoted signal \"altpll0:inst1\|altpll:altpll_component\|_clk1\" to use global clock (user assigned)" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "altpll0:inst1\|altpll:altpll_component\|_clk1" } { 0 "altpll0:inst1\|altpll:altpll_component\|_clk0" } } } } { "net_1c6_911.bdf" "" { Schematic "D:/Test/net_1c6_911/net_1c6_911.bdf" { { -216 64 304 -40 "inst1" "" } } } } { "altpll.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altpll.tdf" 765 3 0 } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "" { altpll0:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "D:/Test/net_1c6_911/net_1c6_911.fld" "" { Floorplan "D:/Test/net_1c6_911/net_1c6_911.fld" "" "" { altpll0:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock (user assigned)" 0 0}  } {  } 0 0 "Promoted PLL clock signals" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "PLL Placement Operation " "Info: Completed PLL Placement Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "altera_internal_jtag~TCKUTAP Global clock " "Info: Automatically promoted signal \"altera_internal_jtag~TCKUTAP\" to use Global clock" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TDO" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } "" } } { "D:/Test/net_1c6_911/net_1c6_911.fld" "" { Floorplan "D:/Test/net_1c6_911/net_1c6_911.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "altera_internal_jtag~UPDATEUSER Global clock " "Info: Automatically promoted signal \"altera_internal_jtag~UPDATEUSER\" to use Global clock" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TDO" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } "" } } { "D:/Test/net_1c6_911/net_1c6_911.fld" "" { Floorplan "D:/Test/net_1c6_911/net_1c6_911.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nios_c6:inst\|nios_c6_reset_clk_domain_synch_module:nios_c6_reset_clk_domain_synch\|data_out Global clock " "Info: Automatically promoted some destinations of signal \"nios_c6:inst\|nios_c6_reset_clk_domain_synch_module:nios_c6_reset_clk_domain_synch\|data_out\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "nios_c6:inst\|sdram_0:the_sdram_0\|active_cs_n " "Info: Destination \"nios_c6:inst\|sdram_0:the_sdram_0\|active_cs_n\" may be non-global or may not use global clock" {  } { { "sdram_0.v" "" { Text "D:/Test/net_1c6_911/sdram_0.v" 201 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "nios_c6:inst\|sdram_0:the_sdram_0\|active_addr\[20\]~506 " "Info: Destination \"nios_c6:inst\|sdram_0:the_sdram_0\|active_addr\[20\]~506\" may be non-global or may not use global clock" {  } { { "sdram_0.v" "" { Text "D:/Test/net_1c6_911/sdram_0.v" 415 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "nios_c6:inst\|sdram_0:the_sdram_0\|active_cs_n~187 " "Info: Destination \"nios_c6:inst\|sdram_0:the_sdram_0\|active_cs_n~187\" may be non-global or may not use global clock" {  } { { "sdram_0.v" "" { Text "D:/Test/net_1c6_911/sdram_0.v" 201 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "nios_c6:inst\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug\|jtag_break " "Info: Destination \"nios_c6:inst\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug\|jtag_break\" may be non-global or may not use global clock" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 463 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "nios_c6:inst\|sdram_0:the_sdram_0\|i_refs\[2\] " "Info: Destination \"nios_c6:inst\|sdram_0:the_sdram_0\|i_refs\[2\]\" may be non-global or may not use global clock" {  } { { "sdram_0.v" "" { Text "D:/Test/net_1c6_911/sdram_0.v" 335 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "nios_c6:inst\|sdram_0:the_sdram_0\|i_refs\[1\] " "Info: Destination \"nios_c6:inst\|sdram_0:the_sdram_0\|i_refs\[1\]\" may be non-global or may not use global clock" {  } { { "sdram_0.v" "" { Text "D:/Test/net_1c6_911/sdram_0.v" 335 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "nios_c6:inst\|sdram_0:the_sdram_0\|i_refs\[0\] " "Info: Destination \"nios_c6:inst\|sdram_0:the_sdram_0\|i_refs\[0\]\" may be non-global or may not use global clock" {  } { { "sdram_0.v" "" { Text "D:/Test/net_1c6_911/sdram_0.v" 335 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "nios_c6:inst\|cpu_0:the_cpu_0\|ic_tag_wren " "Info: Destination \"nios_c6:inst\|cpu_0:the_cpu_0\|ic_tag_wren\" may be non-global or may not use global clock" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 4771 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "nios_c6:inst\|cpu_0:the_cpu_0\|ic_tag_wraddress\[0\]~946 " "Info: Destination \"nios_c6:inst\|cpu_0:the_cpu_0\|ic_tag_wraddress\[0\]~946\" may be non-global or may not use global clock" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 4768 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "nios_c6:inst\|cpu_0:the_cpu_0\|ic_tag_wraddress\[1\]~947 " "Info: Destination \"nios_c6:inst\|cpu_0:the_cpu_0\|ic_tag_wraddress\[1\]~947\" may be non-global or may not use global clock" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 4768 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0 0 "Limited to %1!d! non-global destinations" 0 0}  } { { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 4452 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|CLRN_SIGNAL Global clock " "Info: Automatically promoted some destinations of signal \"sld_hub:sld_hub_inst\|CLRN_SIGNAL\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "nios_c6:inst\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|ir\[1\]~0 " "Info: Destination \"nios_c6:inst\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|ir\[1\]~0\" may be non-global or may not use global clock" {  } { { "cpu_0_jtag_debug_module.v" "" { Text "D:/Test/net_1c6_911/cpu_0_jtag_debug_module.v" 203 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "nios_c6:inst\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug\|resetlatch " "Info: Destination \"nios_c6:inst\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug\|resetlatch\" may be non-global or may not use global clock" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 446 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "nios_c6:inst\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug\|resetlatch~182 " "Info: Destination \"nios_c6:inst\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug\|resetlatch~182\" may be non-global or may not use global clock" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 446 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 316 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] Global clock " "Info: Automatically promoted some destinations of signal \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] " "Info: Destination \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]\" may be non-global or may not use global clock" {  } { { "../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1144 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\] " "Info: Destination \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\]\" may be non-global or may not use global clock" {  } { { "../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1144 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "../../altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1144 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}