net_1c6_911.fit.qmsg

来自「91c111芯片的网络模块的原理图以及和ep1c6fpga连线相关的例子程序」· QMSG 代码 · 共 50 行 · 第 1/5 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version " "Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 26 14:54:31 2006 " "Info: Processing started: Wed Jul 26 14:54:31 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off net_1c6_911 -c net_1c6_911 " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off net_1c6_911 -c net_1c6_911" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "net_1c6_911 EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design \"net_1c6_911\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "ICUT_CUT_YGR_PLL_CAN_ACHIEVE_RATIO_AND_PHASE_SHIFT" "altpll0:inst1\|altpll:altpll_component\|pll " "Info: Implementing parameter values for PLL \"altpll0:inst1\|altpll:altpll_component\|pll\"" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "altpll0:inst1\|altpll:altpll_component\|_clk0 1 1 0 0 " "Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of 0 degrees (0 ps) for altpll0:inst1\|altpll:altpll_component\|_clk0 port" {  } {  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "altpll0:inst1\|altpll:altpll_component\|_clk1 1 1 -27 -1499 " "Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of -27 degrees (-1499 ps) for altpll0:inst1\|altpll:altpll_component\|_clk1 port" {  } {  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0}  } { { "altpll.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altpll.tdf" 765 3 0 } } { "altpll0.v" "" { Text "D:/Test/net_1c6_911/altpll0.v" 54 -1 0 } } { "net_1c6_911.bdf" "" { Schematic "D:/Test/net_1c6_911/net_1c6_911.bdf" { { -216 64 304 -40 "inst1" "" } } } }  } 0 0 "Implementing parameter values for PLL \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C8 " "Info: Device EP1C12Q240C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "4 116 " "Info: No exact pin location assignment(s) for 4 pins of 116 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tdo " "Info: Pin altera_reserved_tdo not assigned to an exact location on the device" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tdo" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "" { altera_reserved_tdo } "NODE_NAME" } "" } } { "D:/Test/net_1c6_911/net_1c6_911.fld" "" { Floorplan "D:/Test/net_1c6_911/net_1c6_911.fld" "" "" { altera_reserved_tdo } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tms " "Info: Pin altera_reserved_tms not assigned to an exact location on the device" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tms" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "" { altera_reserved_tms } "NODE_NAME" } "" } } { "D:/Test/net_1c6_911/net_1c6_911.fld" "" { Floorplan "D:/Test/net_1c6_911/net_1c6_911.fld" "" "" { altera_reserved_tms } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tck " "Info: Pin altera_reserved_tck not assigned to an exact location on the device" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tck" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "" { altera_reserved_tck } "NODE_NAME" } "" } } { "D:/Test/net_1c6_911/net_1c6_911.fld" "" { Floorplan "D:/Test/net_1c6_911/net_1c6_911.fld" "" "" { altera_reserved_tck } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "altera_reserved_tdi " "Info: Pin altera_reserved_tdi not assigned to an exact location on the device" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "altera_reserved_tdi" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "net_1c6_911" "UNKNOWN" "V1" "D:/Test/net_1c6_911/db/net_1c6_911.quartus_db" { Floorplan "D:/Test/net_1c6_911/" "" "" { altera_reserved_tdi } "NODE_NAME" } "" } } { "D:/Test/net_1c6_911/net_1c6_911.fld" "" { Floorplan "D:/Test/net_1c6_911/net_1c6_911.fld" "" "" { altera_reserved_tdi } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}