net_1c6_911.map.qmsg

来自「91c111芯片的网络模块的原理图以及和ep1c6fpga连线相关的例子程序」· QMSG 代码 · 共 135 行 · 第 1/5 页

{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_17_is_x cpu_0_test_bench.v(103) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(103): object \"M_wr_data_unfiltered_17_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 103 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_18_is_x cpu_0_test_bench.v(104) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(104): object \"M_wr_data_unfiltered_18_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 104 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_19_is_x cpu_0_test_bench.v(105) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(105): object \"M_wr_data_unfiltered_19_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 105 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_1_is_x cpu_0_test_bench.v(106) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(106): object \"M_wr_data_unfiltered_1_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 106 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_20_is_x cpu_0_test_bench.v(107) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(107): object \"M_wr_data_unfiltered_20_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 107 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_21_is_x cpu_0_test_bench.v(108) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(108): object \"M_wr_data_unfiltered_21_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 108 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_22_is_x cpu_0_test_bench.v(109) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(109): object \"M_wr_data_unfiltered_22_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 109 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_23_is_x cpu_0_test_bench.v(110) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(110): object \"M_wr_data_unfiltered_23_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 110 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_24_is_x cpu_0_test_bench.v(111) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(111): object \"M_wr_data_unfiltered_24_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 111 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_25_is_x cpu_0_test_bench.v(112) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(112): object \"M_wr_data_unfiltered_25_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 112 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_26_is_x cpu_0_test_bench.v(113) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(113): object \"M_wr_data_unfiltered_26_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 113 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_27_is_x cpu_0_test_bench.v(114) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(114): object \"M_wr_data_unfiltered_27_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 114 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_28_is_x cpu_0_test_bench.v(115) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(115): object \"M_wr_data_unfiltered_28_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 115 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_29_is_x cpu_0_test_bench.v(116) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(116): object \"M_wr_data_unfiltered_29_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 116 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_2_is_x cpu_0_test_bench.v(117) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(117): object \"M_wr_data_unfiltered_2_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 117 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_30_is_x cpu_0_test_bench.v(118) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(118): object \"M_wr_data_unfiltered_30_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 118 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_31_is_x cpu_0_test_bench.v(119) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(119): object \"M_wr_data_unfiltered_31_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 119 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_3_is_x cpu_0_test_bench.v(120) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(120): object \"M_wr_data_unfiltered_3_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 120 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_4_is_x cpu_0_test_bench.v(121) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(121): object \"M_wr_data_unfiltered_4_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 121 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_5_is_x cpu_0_test_bench.v(122) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(122): object \"M_wr_data_unfiltered_5_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 122 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_6_is_x cpu_0_test_bench.v(123) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(123): object \"M_wr_data_unfiltered_6_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 123 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_7_is_x cpu_0_test_bench.v(124) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(124): object \"M_wr_data_unfiltered_7_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 124 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_8_is_x cpu_0_test_bench.v(125) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(125): object \"M_wr_data_unfiltered_8_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 125 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_9_is_x cpu_0_test_bench.v(126) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(126): object \"M_wr_data_unfiltered_9_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 126 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "W_inst cpu_0_test_bench.v(127) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(127): object \"W_inst\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 127 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "W_op_add cpu_0_test_bench.v(128) " "Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(128): object \"W_op_add\" assigned a value but never read" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 128 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "W_op_addi cpu_0_test_bench.v(129) " "Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(129): object \"W_op_addi\" assigned a value but never read" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 129 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}