net_1c6_911.map.qmsg

来自「91c111芯片的网络模块的原理图以及和ep1c6fpga连线相关的例子程序」· QMSG 代码 · 共 135 行 · 第 1/5 页

{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_pcb cpu_0_test_bench.v(67) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(67): object \"M_pcb\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 67 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_st_data cpu_0_test_bench.v(68) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(68): object \"M_st_data\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 68 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_status_reg cpu_0_test_bench.v(69) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(69): object \"M_status_reg\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 69 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_valid cpu_0_test_bench.v(70) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(70): object \"M_valid\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 70 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_dst_reg cpu_0_test_bench.v(72) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(72): object \"M_wr_dst_reg\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 72 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "W_dst_regnum cpu_0_test_bench.v(73) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(73): object \"W_dst_regnum\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 73 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "W_iw cpu_0_test_bench.v(74) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(74): object \"W_iw\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 74 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "W_pcb cpu_0_test_bench.v(77) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(77): object \"W_pcb\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 77 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "W_valid cpu_0_test_bench.v(78) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(78): object \"W_valid\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 78 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "W_wr_data cpu_0_test_bench.v(79) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(79): object \"W_wr_data\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 79 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "W_wr_dst_reg cpu_0_test_bench.v(80) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(80): object \"W_wr_dst_reg\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 80 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "d_address cpu_0_test_bench.v(82) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(82): object \"d_address\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 82 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "d_byteenable cpu_0_test_bench.v(83) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(83): object \"d_byteenable\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 83 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "d_read cpu_0_test_bench.v(84) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(84): object \"d_read\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 84 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "d_write cpu_0_test_bench.v(85) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(85): object \"d_write\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 85 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "i_address cpu_0_test_bench.v(86) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(86): object \"i_address\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 86 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "i_read cpu_0_test_bench.v(87) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(87): object \"i_read\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 87 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "i_readdatavalid cpu_0_test_bench.v(88) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(88): object \"i_readdatavalid\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 88 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "M_target_pcb cpu_0_test_bench.v(93) " "Warning (10036): Verilog HDL or VHDL warning at cpu_0_test_bench.v(93): object \"M_target_pcb\" assigned a value but never read" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 93 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_0_is_x cpu_0_test_bench.v(95) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(95): object \"M_wr_data_unfiltered_0_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 95 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_10_is_x cpu_0_test_bench.v(96) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(96): object \"M_wr_data_unfiltered_10_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 96 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_11_is_x cpu_0_test_bench.v(97) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(97): object \"M_wr_data_unfiltered_11_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 97 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_12_is_x cpu_0_test_bench.v(98) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(98): object \"M_wr_data_unfiltered_12_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 98 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_13_is_x cpu_0_test_bench.v(99) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(99): object \"M_wr_data_unfiltered_13_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 99 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_14_is_x cpu_0_test_bench.v(100) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(100): object \"M_wr_data_unfiltered_14_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 100 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_15_is_x cpu_0_test_bench.v(101) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(101): object \"M_wr_data_unfiltered_15_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 101 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_wr_data_unfiltered_16_is_x cpu_0_test_bench.v(102) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(102): object \"M_wr_data_unfiltered_16_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 102 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}