net_1c6_911.map.qmsg

来自「91c111芯片的网络模块的原理图以及和ep1c6fpga连线相关的例子程序」· QMSG 代码 · 共 135 行 · 第 1/5 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version " "Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 26 14:50:58 2006 " "Info: Processing started: Wed Jul 26 14:50:58 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off net_1c6_911 -c net_1c6_911 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off net_1c6_911 -c net_1c6_911" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "net_1c6_911.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file net_1c6_911.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 net_1c6_911 " "Info: Found entity 1: net_1c6_911" {  } { { "net_1c6_911.bdf" "" { Schematic "D:/Test/net_1c6_911/net_1c6_911.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "net_1c6_911 " "Info: Elaborating entity \"net_1c6_911\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "nios_c6.v 17 17 " "Warning: Using design file nios_c6.v, which is not specified as a design file for the current project, but contains definitions for 17 design units and 17 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_0_jtag_debug_module_arbitrator " "Info: Found entity 1: cpu_0_jtag_debug_module_arbitrator" {  } { { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 25 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 cpu_0_data_master_arbitrator " "Info: Found entity 2: cpu_0_data_master_arbitrator" {  } { { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 411 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 cpu_0_instruction_master_arbitrator " "Info: Found entity 3: cpu_0_instruction_master_arbitrator" {  } { { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 807 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "4 epcs_controller_epcs_control_port_arbitrator " "Info: Found entity 4: epcs_controller_epcs_control_port_arbitrator" {  } { { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 1186 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "5 jtag_uart_0_avalon_jtag_slave_arbitrator " "Info: Found entity 5: jtag_uart_0_avalon_jtag_slave_arbitrator" {  } { { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 1575 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "6 led_pio_s1_arbitrator " "Info: Found entity 6: led_pio_s1_arbitrator" {  } { { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 1825 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "7 rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module " "Info: Found entity 7: rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module" {  } { { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 2029 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "8 rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module " "Info: Found entity 8: rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module" {  } { { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 2358 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "9 sdram_0_s1_arbitrator " "Info: Found entity 9: sdram_0_s1_arbitrator" {  } { { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 2687 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "10 sys_clk_timer_s1_arbitrator " "Info: Found entity 10: sys_clk_timer_s1_arbitrator" {  } { { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 3140 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "11 sysid_control_slave_arbitrator " "Info: Found entity 11: sysid_control_slave_arbitrator" {  } { { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 3360 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "12 tri_state_bridge_0_avalon_slave_arbitrator " "Info: Found entity 12: tri_state_bridge_0_avalon_slave_arbitrator" {  } { { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 3546 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "13 tri_state_bridge_0_bridge_arbitrator " "Info: Found entity 13: tri_state_bridge_0_bridge_arbitrator" {  } { { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 4433 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "14 nios_c6_reset_clk_domain_synch_module " "Info: Found entity 14: nios_c6_reset_clk_domain_synch_module" {  } { { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 4441 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "15 nios_c6 " "Info: Found entity 15: nios_c6" {  } { { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 4481 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "16 flash_lane0_module " "Info: Found entity 16: flash_lane0_module" {  } { { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 5270 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "17 flash " "Info: Found entity 17: flash" {  } { { "nios_c6.v" "" { Text "D:/Test/net_1c6_911/nios_c6.v" 5356 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "nios_c6 nios_c6:inst " "Info: Elaborating entity \"nios_c6\" for hierarchy \"nios_c6:inst\"" {  } { { "net_1c6_911.bdf" "inst" { Schematic "D:/Test/net_1c6_911/net_1c6_911.bdf" { { 40 264 648 472 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_jtag_debug_module_arbitrator nios_c6:inst\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module " "Info: Elaborating entity \"cpu_0_jtag_debug_module_arbitrator\" for hierarchy \"nios_c6:inst\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\"" {  } { { "nios_c6.v" "the_cpu_0_jtag_debug_module" { Text "D:/Test/net_1c6_911/nios_c6.v" 4731 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_data_master_arbitrator nios_c6:inst\|cpu_0_data_master_arbitrator:the_cpu_0_data_master " "Info: Elaborating entity \"cpu_0_data_master_arbitrator\" for hierarchy \"nios_c6:inst\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\"" {  } { { "nios_c6.v" "the_cpu_0_data_master" { Text "D:/Test/net_1c6_911/nios_c6.v" 4769 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_instruction_master_arbitrator nios_c6:inst\|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master " "Info: Elaborating entity \"cpu_0_instruction_master_arbitrator\" for hierarchy \"nios_c6:inst\|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master\"" {  } { { "nios_c6.v" "the_cpu_0_instruction_master" { Text "D:/Test/net_1c6_911/nios_c6.v" 4855 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "cpu_0.v 26 26 " "Warning: Using design file cpu_0.v, which is not specified as a design file for the current project, but contains definitions for 26 design units and 26 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_0_ic_data_module " "Info: Found entity 1: cpu_0_ic_data_module" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 20 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 cpu_0_ic_tag_module " "Info: Found entity 2: cpu_0_ic_tag_module" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 117 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 cpu_0_register_bank_a_module " "Info: Found entity 3: cpu_0_register_bank_a_module" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 216 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "4 cpu_0_register_bank_b_module " "Info: Found entity 4: cpu_0_register_bank_b_module" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 315 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "5 cpu_0_nios2_oci_debug " "Info: Found entity 5: cpu_0_nios2_oci_debug" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 414 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "6 cpu_0_ociram_lpm_dram_bdp_component_module " "Info: Found entity 6: cpu_0_ociram_lpm_dram_bdp_component_module" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 526 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "7 cpu_0_nios2_ocimem " "Info: Found entity 7: cpu_0_nios2_ocimem" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 611 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "8 cpu_0_nios2_avalon_reg " "Info: Found entity 8: cpu_0_nios2_avalon_reg" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 749 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "9 cpu_0_nios2_oci_break " "Info: Found entity 9: cpu_0_nios2_oci_break" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 835 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "10 cpu_0_nios2_oci_xbrk " "Info: Found entity 10: cpu_0_nios2_oci_xbrk" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 1305 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "11 cpu_0_nios2_oci_match_paired " "Info: Found entity 11: cpu_0_nios2_oci_match_paired" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 1537 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "12 cpu_0_nios2_oci_match_single " "Info: Found entity 12: cpu_0_nios2_oci_match_single" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 1567 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "13 cpu_0_nios2_oci_dbrk " "Info: Found entity 13: cpu_0_nios2_oci_dbrk" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 1595 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "14 cpu_0_nios2_oci_itrace " "Info: Found entity 14: cpu_0_nios2_oci_itrace" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 1818 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "15 cpu_0_nios2_oci_td_mode " "Info: Found entity 15: cpu_0_nios2_oci_td_mode" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 2086 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "16 cpu_0_nios2_oci_dtrace " "Info: Found entity 16: cpu_0_nios2_oci_dtrace" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 2145 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "17 cpu_0_nios2_oci_compute_tm_count " "Info: Found entity 17: cpu_0_nios2_oci_compute_tm_count" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 2230 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "18 cpu_0_nios2_oci_fifowp_inc " "Info: Found entity 18: cpu_0_nios2_oci_fifowp_inc" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 2293 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "19 cpu_0_nios2_oci_fifocount_inc " "Info: Found entity 19: cpu_0_nios2_oci_fifocount_inc" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 2327 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "20 cpu_0_nios2_oci_fifo " "Info: Found entity 20: cpu_0_nios2_oci_fifo" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 2365 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "21 cpu_0_nios2_oci_pib " "Info: Found entity 21: cpu_0_nios2_oci_pib" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 2845 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "22 cpu_0_traceram_lpm_dram_bdp_component_module " "Info: Found entity 22: cpu_0_traceram_lpm_dram_bdp_component_module" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 2905 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "23 cpu_0_nios2_oci_im " "Info: Found entity 23: cpu_0_nios2_oci_im" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 2986 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "24 cpu_0_nios2_performance_monitors " "Info: Found entity 24: cpu_0_nios2_performance_monitors" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 3115 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "25 cpu_0_nios2_oci " "Info: Found entity 25: cpu_0_nios2_oci" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 3123 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "26 cpu_0 " "Info: Found entity 26: cpu_0" {  } { { "cpu_0.v" "" { Text "D:/Test/net_1c6_911/cpu_0.v" 3638 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0 nios_c6:inst\|cpu_0:the_cpu_0 " "Info: Elaborating entity \"cpu_0\" for hierarchy \"nios_c6:inst\|cpu_0:the_cpu_0\"" {  } { { "nios_c6.v" "the_cpu_0" { Text "D:/Test/net_1c6_911/nios_c6.v" 4903 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "cpu_0_test_bench.v 1 1 " "Warning: Using design file cpu_0_test_bench.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_0_test_bench " "Info: Found entity 1: cpu_0_test_bench" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_test_bench nios_c6:inst\|cpu_0:the_cpu_0\|cpu_0_test_bench:the_cpu_0_test_bench " "Info: Elaborating entity \"cpu_0_test_bench\" for hierarchy \"nios_c6:inst\|cpu_0:the_cpu_0\|cpu_0_test_bench:the_cpu_0_test_bench\"" {  } { { "cpu_0.v" "the_cpu_0_test_bench" { Text "D:/Test/net_1c6_911/cpu_0.v" 4784 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "E_valid cpu_0_test_bench.v(53) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(53): object \"E_valid\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 53 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_alu_result cpu_0_test_bench.v(54) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(54): object \"M_alu_result\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 54 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_bstatus_reg cpu_0_test_bench.v(55) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(55): object \"M_bstatus_reg\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 55 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_cmp_result cpu_0_test_bench.v(56) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(56): object \"M_cmp_result\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 56 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_ctrl_ld_non_io cpu_0_test_bench.v(57) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(57): object \"M_ctrl_ld_non_io\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 57 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_dst_regnum cpu_0_test_bench.v(58) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(58): object \"M_dst_regnum\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 58 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_estatus_reg cpu_0_test_bench.v(60) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(60): object \"M_estatus_reg\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 60 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_ienable_reg cpu_0_test_bench.v(61) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(61): object \"M_ienable_reg\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 61 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_ipending_reg cpu_0_test_bench.v(62) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(62): object \"M_ipending_reg\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 62 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_iw cpu_0_test_bench.v(63) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(63): object \"M_iw\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 63 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_mem_byte_en cpu_0_test_bench.v(64) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(64): object \"M_mem_byte_en\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 64 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_op_hbreak cpu_0_test_bench.v(65) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(65): object \"M_op_hbreak\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 65 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "M_op_intr cpu_0_test_bench.v(66) " "Info (10035): Verilog HDL or VHDL information at cpu_0_test_bench.v(66): object \"M_op_intr\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "D:/Test/net_1c6_911/cpu_0_test_bench.v" 66 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}